In a doubly-resonant coil there is nothing to limit the primary current. The tank capacitor cancels the primary's reactance and the resistance reflected back from the secondary is small until there is an arc out. Without protection the coil destroys itself, and it does not take long.
Two behaviours, and they are not interchangeable
Both sit on the same board and the choice between them is a solder jumper. WaskaLabs' UD2.9X documents the pair in one paragraph, and its wording is the plainest statement of the difference anybody has published:
- OCD ends the bang there and then. On a trip "the pulse ends and goes back to steady state until the next interrupter pulse occurs."
- Pulse skip lets the bang carry on, limiting "your peak current values without killing the pulse completely by skipping a single oscillation on the bridge during operation."
The board ships in OCD and the SKIP_EN solder jumper on its back is what changes that. The skip circuit itself is credited on the same page to Daniel Marks' through-hole UD2.9 (profdc9/DRSSTC-PCB-Pack).
And the manual's case for skipping does not carry to a ramp
That case is a length of time. Skipping "allows you to have increasingly long pulse durations (100s of uS to multiple mS) without exceeding the primary current you set." A QCW's ramp is exactly that length, and this page used to read the sentence straight and conclude that a QCW therefore wants pulse skip. That conclusion was wrong, and it was this page's load-bearing error.
Length is not the only thing a ramp has. It also has a bus voltage that is still climbing and a pole pair that is still moving, so a skip does not return the machine to the conditions it left. Three live pages already say so and this one now agrees with them: the buck's page puts it in a line, that a QCW wants ordinary latching overcurrent and not pulse skip; the QCW arc's page works out why, that skipping resumes into a different machine and does it again for the rest of the ramp; and the conversion page reads the same manual and lands in the same place. On a ramp, "until the next interrupter pulse" means until the next flash, so latching costs exactly one bang and buys a predictable end to it.
The pop you can hear is real, and it is not an argument for skipping. What Gao Guangyan noticed on his first QCW is that a controlled ramp-down leaves the spark much quieter while an OCD trip "ends with a harsher bang sound" (loneoceans). A trip that arrives before the ramp has finished is the threshold being reached too early, and the commonest reason for that is a tank capacitor that is too big. The cure is the capacitor, not the protection mode.
And do not confuse either of these with pulse skip as a way of shaping a ramp. Here it is protection. As a replacement for a buck modulator it has been tried three times in public, by Steve Conner in 2011, by Steve Ward on the UD3 and by Chris Dickey (HVF 292), and nobody got a sword out of it. That attempt belongs with the modulator.
A third behaviour, which is current handling rather than protection
Between ending the bang and dropping one cycle of it there is a third thing, and the boards that do it call it freewheeling. Over current the bridge is not shut down: the current is left to circulate through devices that stay on, so the bang continues and the switches share the work. The UD+ does this, and it is why a freewheeling bridge wants two gate transformers rather than one, since the legs have to be driven independently when the devices turn off in turn rather than together.
A schematic for the second, on 74AC logic, is worked out on kechuang (t/83521, t/83545). Opening the switches in turn rather than together sends the current through the upper and lower pairs in alternation, so the heat is shared across all four rather than cooked into one pair. Gao does the same thing for the same reason on a different technique: under phase shift "half the bridge is always switched in resonance and half doing hard switching", and to share that load "the driver goes one step further to alternate hard switching between the two halves every cycle."
It needs its own current transformer
Two jobs, two rings. The feedback ring has the phase lead network hanging off it, that network loads the first stage, the core saturates, and the protection goes soft exactly when it is needed. That argument and the arithmetic under it are the current transformer's own page, and they are why the DRSSTC diagram draws two rings where the SSTC draws one.
Sharing is not simply a mistake, though, and saying so flatly was one of this page's errors. The UD3's specification puts one input on both jobs by design, "Current transformer input for gate drive synchronization and current limiting", as the page above reads it out, and it pays for that in sensitivity rather than in a saturating core: one network now has to reach the trip current without running the comparator out of range, so it sits about an order of magnitude below the band a feedback-only ring works in.
Steve Conner shared one ring deliberately long before that, and published the trick that makes it behave: two back-to-back diodes in series with the burden, with the overcurrent tap taken "across the burden alone" and the feedback tap "across the burden and the diodes", which "gives a better signal at low primary currents" without moving the trip point (PLL driver manual). If you are going to share, share like that.
The UD2.9X assumes two and tells you how to build the second: "your OCD CT should be wound the same as your Feedback CT", with the overcurrent one rectified into the reference, so unlike the feedback ring it needs no phasing at all.
A comparator, not a Schmitt trigger
Do not use a 74HC14 for current protection. A logic trigger's thresholds move with temperature and supply, and this is the one place that needs a threshold you can predict. The argument belongs to inside the driver and it covers both of the driver's decisions, not only this one.
What the boards actually fit is worth knowing, because the part decides what the ring has to deliver. davekni names two on HVF 1804: "TLV3501 is the part I use for high-speed comparison", and "The UD2.7 uses TL3116". The UD2.9X fits an LM311D and states its range in the same breath as the setting procedure: the part is "capable of comparing up to 12V at its highest threshold", and the board asks you to wind the transformer so the burden voltage stays between 2 and 10 V. Both ends of that range matter, and running off the top of it is one of the ways the list below goes silent.
Why it did not fire
- The threshold is far above the dial. The burden resistor is not the one the scale was calculated for. The two on a UD board are a factor of ten apart, and a scale drawn for one of them means nothing on the other.
- Protection exists and has never once operated. The pot is wound past anything the ring can deliver, which means it is switched off. Two designers say so about their own boards. Steve Conner's PLL driver manual sets the limit by measuring across a trimmer and then shouts the failure: "DO NOT adjust it to more than 9V or the limiter may never kick in at all!", and his own errata records a clamping change that left the limiter "totally non-functional if it is set higher than 450A" (PLL driver manual). On the UD2.9X the reference is measurable on the
OCD_REFpin against ground, so on that board this is answerable with a multimeter before the coil is ever fired. - It fires late and the switches are already dead. The threshold has to sit below the destructive current rather than at it. Two different reasons for the lateness sit in the two boards above, and neither is the comparator. The UD2.9X rectifies the overcurrent ring's output into the reference, so what is compared is a held value rather than the instantaneous current. Conner's compares the raw burden voltage against a window, and then stops the drive on whole cycles, "synchronised to whole cycles too". Either way the answer arrives in cycles rather than in nanoseconds. How many cycles is this corpus's estimate of a chain nobody here has measured, and the ground strike page prices a few of them on its reference machine: about 8.6 µs at its working frequency, in which a bridge that has lost lock overshoots the set point by about 1.6 times.
- It got weaker after the phase lead went in. Shared ring, saturating core.
Where to set it
Start low and raise it as you learn, which is what Gao Guangyan did across two machines. He ran the first with "OCD conservatively set at around 120 - 125A" and measured about 126 A at the peak of the ramp, just under it (loneoceans). On QCW 1.5 a year later he had it "to just over 150A" as a bid to stay "within" the 75 A pulse rating per IGBT, and found that "this was about the maximum ramp I could use before hitting the current limit"; the experiment after that ran with the limit "around 160A" and the primary hovering between 145 and 160 A (loneoceans). Four settings across two machines, walked upwards, every one of them read off the coil rather than calculated for it.
That is the right way round, because the threshold is not a number you arrive with. The primary's own page records a case where a calculated primary current and a measured one were far enough apart to end the project, and it carries both figures. This page used to repeat them and no longer does: no published thread for them has been found from here, and the forum whose threads would settle it answers with a server error. The same page is worth reading for the other half of the question, which is that a coil can be impedance-limited rather than OCD-limited, and on such a coil the threshold is decoration whatever you set it to.
The threshold is set by the primary, the capacitors and the coupling, not by the power you would like to have.
How the capacitors set it, which is through burst length
That sentence names the capacitors and does not say how they do it. The link is the tank voltage, and the tank voltage is not a fixed thing you can look up: it rings up as the burst runs. Each half cycle the inverter reverses, it adds to what is already there, so a longer burst leaves more volts across the capacitors and more current in the primary. The threshold and the maximum ontime are one question asked twice.
Matt "Sigurthr" Giordano's method starts from that, and it is written up in Barnkob's MMC chapter. Take the string's rating, de-rate it, and work backwards to the current the detector may allow. His own worked case is six parallel strings of two CDE 942C20P15K-F at 2000 V, so 4000 V a string, de-rated by 20 per cent to 3200 V. That allows 472 A of primary peak, and he says plainly what it is for: it is why his DRSSTC 1 ran with the detector at 500 A, which was as low as the rating asked and no lower than the switches wanted.
Then the ontime that reaches it, and here the bridge topology halves the answer:
70 kHz, 3200 V ceiling, 472 A
half bridge 10 half cycles about 72 us
full bridge 5 half cycles about 35 usThat is arithmetic rather than a rule, and it checks: a half period at 70 kHz is 7.14 µs, ten of them 71 µs and five of them 36 µs [derived]. A full bridge adds voltage twice as fast per unit time, so it arrives at the same ceiling in half the burst.
When the arc strikes ground
The topload voltage collapses fast, and the figure this corpus quotes for it had lost its source. Here it is. Steve Ward, quoted by Paul Nicholson on the Tesla Coil Mailing List in September 2012: "During a ground discharge, the voltage at the topload has been measured to collapse within 100nS (worst case) and 250nS (more typical)" (pupman archive). This page and what RF ground is both carried the 100 to 250 ns without one, and the arc growth page says so in a note. That note can come down.
The mechanism is Steve Ward's too, on the thread that carries the only measured strike resistance anybody has published (HVF 117): a ground arc is so low a resistance beside the secondary's impedance that the secondary stops behaving as an LC and becomes an inductance with a resistance across it. Once that has happened there is nothing resonant for the primary to deliver into, and the primary's own current goes up rather than down.
Whether the detector answers is then the threshold rather than the strike. On that same modelled machine, a threshold a fifth over the normal ramp fires the moment the channel establishes, and one half again over is never reached by the only strike anybody has published: Hydron's, on a 160 mm secondary and therefore another coil again, where the load goes from capacitive to resistive and bottoms out around 25 kΩ on the thread above. One measurement, sitting between two settings a builder might reasonably choose.
There is a second route to the threshold, faster and by a different mechanism altogether, and it is the one that trips real machines. The secondary jumps to a harmonic of its own resonance, the switching loses sync, and the primary stops being part of a tuned tank at all. That is worked through on the same page, and between the delay above and that route, the protection meets the event after it rather than at it.
A ceiling in firmware is not protection
The rest of the safety chain
- UVLO, because when the supply sags the digital isolators emit a spike that turns both devices in a leg on, and that is shoot-through.
- Fail-safe on the fibre. A broken fibre must turn the coil off, and the receiver does not do that by itself. Its output is defined in the dark, and on the reference board the resistor on that input holds it at on. A defined level is not a safe one.
- A bleeder across the bus bank. Not optional, and it wants a size rather than a presence.
- A duty cycle limit in the interrupter, which is the wall the skip jumper walks you into.
The two rings on the DRSSTC diagram are this and the feedback one, drawn separately because that is the point. Take the tank capacitor out on the QCW page and the overcurrent ring goes with it: nothing is cancelling the primary's reactance any more, so the primary's own impedance is the limit.