In a doubly-resonant coil nothing limits the primary current. The tank capacitor cancels the primary's reactance, and the resistance reflected back from the secondary stays small until an arc is out. Without overcurrent protection the coil destroys itself, quickly.
Two behaviours, and they are not interchangeable
On WaskaLabs' UD2.9X the two responses to an overcurrent trip sit on the same board, chosen with a solder jumper. Its documentation describes the pair in one paragraph, and it is the clearest published statement of the difference:
- OCD ends the bang there and then. On a trip "the pulse ends and goes back to steady state until the next interrupter pulse occurs."
- Pulse skip lets the bang carry on, limiting "your peak current values without killing the pulse completely by skipping a single oscillation on the bridge during operation."
The board ships in OCD, and the SKIP_EN solder jumper on its back changes that. The skip circuit itself is credited on the same page to Daniel Marks' through-hole UD2.9 (profdc9/DRSSTC-PCB-Pack).
And the manual's case for skipping does not carry to a ramp
The manual argues for skipping on pulse length. Skipping "allows you to have increasingly long pulse durations (100s of uS to multiple mS) without exceeding the primary current you set." A QCW's ramp is that long, so read on its own the sentence suggests a QCW wants pulse skip. That conclusion is wrong.
A ramp also has a bus voltage that is still climbing and a pole pair that is still moving, so after a skip the machine does not come back to the conditions it left. Three other articles agree on this. The buck article says a QCW wants ordinary latching overcurrent and not pulse skip. The QCW arc article works out why: skipping resumes into a different machine, and keeps doing so for the rest of the ramp. The conversion article reads the same manual and reaches the same answer. On a ramp, "until the next interrupter pulse" means until the next flash, so latching costs one bang and gives it a predictable end.
The pop you hear on a trip is real, but it is no reason to skip. Gao Guangyan noticed on his first QCW that a controlled ramp-down leaves the spark much quieter, while an OCD trip "ends with a harsher bang sound" (loneoceans). A trip before the ramp has finished means the threshold is being reached too early, and the commonest reason is a tank capacitor that is too big. Fix the capacitor, not the protection mode.
Pulse skip as protection is also a different thing from pulse skip used to shape a ramp. As a replacement for a buck modulator it has been tried three times in public, by Steve Conner in 2011, by Steve Ward on the UD3 and by Chris Dickey (HVF 292), and none of them got a sword out of it. That story is told with the modulator.
A third behaviour, which is current handling rather than protection
Some boards do a third thing on overcurrent, which they call freewheeling. The bridge is not shut down. The current circulates through devices that stay on, so the bang continues and the switches share the work. The UD+ does this. A freewheeling bridge needs two gate transformers rather than one, because the legs have to be driven independently when the devices turn off in turn rather than together.
The word is used for two different circuits. Gao's QCW 2 calls it free-wheeling to "pause" the inverter and "allow current to flow back to the bus via the reverse diodes as the current rings down, then occasionally driving the primary again", which "allows long pulse durations without exceeding the current limit" (loneoceans). That returns the energy to the bank through the diodes. In the UD+ sense the current stays inside the bridge and never reaches the diodes, and only that version takes the load off the body diodes.
A schematic for the UD+ kind, on 74AC logic, is worked out on kechuang (t/83521, t/83545). Opening the switches in turn rather than together sends the current through the upper and lower pairs in alternation, so the heat is shared across all four instead of cooking one pair. Gao does the same for the same reason with a different technique. Under phase shift "half the bridge is always switched in resonance and half doing hard switching", and to share that load "the driver goes one step further to alternate hard switching between the two halves every cycle."
None of this is known to lengthen an arc. A version in circulation says the falling edge of each cycle only sustains the channel and adds nothing to its length, so holding the energy in the bridge stretches the sustaining phase. That rests on the idea that a QCW streamer grows on one half of the oscillation only. The idea is Steve Ward's, offered on HVF 117 in his own word as a "theory" for un-branching streamers, and it has been never tested by anybody. The device-stress reasons above hold without it. The arc-length reason does not hold at all.
True per-pulse modulation is a separate case that the driver write-ups do not cover. Dropping individual half cycles regulates the load better and returns the current through the devices, but then the positive pulses are never exactly as many as the negative. A gate transformer's average voltage has to be zero or direct current climbs in the primary loop until the core saturates, so unequal counts walk it into one-sided saturation. That follows from the rule and needs no measurement. An isolated driver per switch cures it but narrows what the board can drive. So the production skip boards work per cycle instead, locking the whole bridge and letting the tank ring down into the supply. Conner's limiter says so directly, that its start-stop events are "synchronised to whole cycles too". That is not the true PDM it is often called.
It needs its own current transformer
The feedback and overcurrent jobs want separate rings. The feedback ring has the phase lead network hanging off it, that network loads the first stage, the core saturates, and the protection goes soft exactly when it is needed. The argument and the arithmetic are on the current transformer's own page, and they are why the DRSSTC diagram draws two rings where the SSTC draws one.
Sharing one ring can still be done on purpose. The UD3's specification puts one input on both jobs by design, "Current transformer input for gate drive synchronization and current limiting", as the page above quotes it. It pays in sensitivity rather than in a saturating core: one network has to reach the trip current without running the comparator out of range, so it sits about an order of magnitude below the band a feedback-only ring works in.
Steve Conner shared one ring deliberately long before that, and published the trick that makes it work: two back-to-back diodes in series with the burden, with the overcurrent tap taken "across the burden alone" and the feedback tap "across the burden and the diodes", which "gives a better signal at low primary currents" without moving the trip point (PLL driver manual). If you are going to share, do it that way.
The UD2.9X assumes two and tells you how to build the second: "your OCD CT should be wound the same as your Feedback CT", with the overcurrent one rectified into the reference, so unlike the feedback ring it needs no phasing at all.
A comparator, not a Schmitt trigger
Do not use a 74HC14 for current protection. A logic trigger's thresholds move with temperature and supply, and the trip point needs a threshold you can predict. The full argument is in inside the driver, and it covers both of the driver's decisions, not only this one.
The part the boards fit matters, because it sets what the ring has to deliver. davekni names two on HVF 1804: "TLV3501 is the part I use for high-speed comparison", and "The UD2.7 uses TL3116". The UD2.9X fits an LM311D and gives its range alongside the setting procedure: the part is "capable of comparing up to 12V at its highest threshold", and the board asks you to wind the transformer so the burden voltage stays between 2 and 10 V. Both ends of that range matter, and going off the top of it is one of the ways the protection goes silent in the list below.
Why it did not fire
- The threshold is far above the dial. The burden resistor is not the one the scale was calculated for. The two on a UD board are a factor of ten apart, and a scale drawn for one of them means nothing on the other.
- Protection exists and has never once operated. The pot is set past anything the ring can deliver, which means it is switched off. Two designers say so about their own boards. Steve Conner's PLL driver manual sets the limit by measuring across a trimmer and then shouts the failure: "DO NOT adjust it to more than 9V or the limiter may never kick in at all!", and his own errata records a clamping change that left the limiter "totally non-functional if it is set higher than 450A" (PLL driver manual). On the UD2.9X the reference is measurable on the
OCD_REFpin against ground, so on that board you can check it with a multimeter before the coil is ever fired. - It fires late and the switches are already dead. The threshold has to sit below the destructive current rather than at it. The two boards above are late for two different reasons, and neither is the comparator. The UD2.9X rectifies the overcurrent ring's output into the reference, so it compares a held value rather than the instantaneous current. Conner's compares the raw burden voltage against a window, and then stops the drive on whole cycles, "synchronised to whole cycles too". Either way the response comes in cycles rather than nanoseconds. How many cycles is our estimate of a chain we have not measured, and the ground strike page puts numbers on a few of them for its reference machine: about 8.6 µs at its working frequency, in which a bridge that has lost lock overshoots the set point by about 1.6 times.
- It got weaker after the phase lead went in. Shared ring, saturating core.
Test the actual threshold, not the position of the knob.
Every reason above is a detector left silent by its own setup, and all of it can be fixed on the bench. Whether a correctly set detector answers a ground strike is a separate question. The answer depends on the number you chose more than on the strike, and it is covered on its own page.
Where to set it
Start low and raise it as you learn, which is what Gao Guangyan did across two machines. He ran the first with "OCD conservatively set at around 120 - 125A" and measured about 126 A at the peak of the ramp, just under it (loneoceans). On QCW 1.5 a year later he had it "to just over 150A" as a bid to stay "within" the 75 A pulse rating per IGBT, and found that "this was about the maximum ramp I could use before hitting the current limit". The experiment after that ran with the limit "around 160A" and the primary hovering between 145 and 160 A (loneoceans). Four settings across two machines, raised step by step, each read off the coil rather than calculated in advance.
That is the right order, because you can't work out the threshold before the coil runs. The primary article records a case where a calculated primary current and a measured one were far enough apart to end the project, and it gives both figures. They are not repeated here, because no published thread for them has been found and the forum that would hold it returns a server error. The same article covers the other half of the question. A coil can be impedance-limited rather than OCD-limited, and on such a coil the threshold does nothing whatever you set it to.
The threshold is set by the primary, the capacitors and the coupling, not by the power you would like to have.
How the capacitors set it, which is through burst length
The capacitors act through the tank voltage, and the tank voltage is not a fixed figure you can look up. It rings up as the burst runs. Each half cycle the inverter reverses, it adds to what is already there, so a longer burst leaves more volts across the capacitors and more current in the primary. The threshold and the maximum ontime are the same question.
So the bank puts a ceiling on the setting. The peak voltage across the tank is the primary current times the capacitor's reactance, V = I / (2π f C), so the string's rating, de-rated, is also a primary current the detector must not allow. The ontime that reaches it depends on the bridge. A full bridge adds twice the voltage per half cycle that a half bridge does, so it reaches the same ceiling in half the burst. Treat that as an upper bound, not the working point. The coil decides where it actually sits, which is the impedance-limited case above.
When the arc strikes ground
The topload voltage collapses fast. The figure for it is Steve Ward's, quoted by Paul Nicholson on the Tesla Coil Mailing List in September 2012: "During a ground discharge, the voltage at the topload has been measured to collapse within 100nS (worst case) and 250nS (more typical)" (pupman archive). The same 100 to 250 ns appears in what RF ground is and in the arc growth page, and this is its source.
The mechanism is Steve Ward's too, on the thread that carries the only measured strike resistance anyone has published (HVF 117). A ground arc is such a low resistance beside the secondary's impedance that the secondary stops behaving as an LC and becomes an inductance with a resistance across it. After that there is nothing resonant for the primary to deliver into, and the primary's own current goes up, not down.
It is widely said that a QCW's primary current drops when the arc reaches earth, the reverse of what an ordinary DRSSTC does. It goes up. Loading a coil harder does at first pull the primary current down, but that fall is used up before the strike arrives. On the machine modelled in the ground strike article, the turn sits near 41 kΩ of total load and an ordinary 1.5 m arc already presents 50, so a real coil starts near the minimum and goes up from there. What a ground strike does to a DRSSTC works the whole curve, and the two figures above belong to that machine, not to coils in general.
Whether the detector answers then depends on the threshold more than on the strike. On that same modelled machine, a threshold a fifth over the normal ramp fires the moment the channel establishes. One half again over is never reached by the only strike anyone has published: Hydron's, on a 160 mm secondary and therefore another coil again, where the load goes from capacitive to resistive and bottoms out around 25 kΩ on the thread above. That is one measurement, sitting between two settings a builder might reasonably choose.
There is a second, faster route to the threshold by a different mechanism, and it is the one that trips real machines. The secondary jumps to a harmonic of its own resonance, the switching loses sync, and the primary stops being part of a tuned tank at all. That is worked through on the same page. Between the delay above and that route, the protection responds after the event rather than at it.
A ceiling in firmware is not protection
The rest of the safety chain
- UVLO, because when the supply sags the digital isolators emit a spike that turns both devices in a leg on, and that is shoot-through.
- Fail-safe on the fibre. A broken fibre must turn the coil off, and the receiver does not do that by itself. Its output is defined in the dark, and on the reference board the resistor on that input holds it at on. A defined level is not a safe one.
- A bleeder across the bus bank. Not optional, and it has to be sized, not just present.
- A duty cycle limit in the interrupter, which is the limit the skip jumper can push you into.
The two rings on the DRSSTC diagram are this one and the feedback one, drawn separately on purpose. Take the tank capacitor out on the QCW page and the overcurrent ring goes with it: nothing is cancelling the primary's reactance any more, so the primary's own impedance is the limit.