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Converting a DRSSTC driver to run a ramp

QCW

What actually has to be touched and why, so that nobody has to work it out by removing components until something changes.

A standard DRSSTC driver will not run a QCW. Here is what actually has to be touched and why, so that nobody has to work it out by removing components until something changes.

The list

  • A starting oscillator, or self-oscillation. To reach and hold the upper pole. Mandatory if you are going up there.
  • Pulse skip instead of cutting the bang on overcurrent. Cutting a ramp in the middle gives a pop instead of a sword. Effectively mandatory.
  • A smaller burden resistor, so the feedback strength lands in its working window of 0.02 to 0.04 V/A. Mandatory.
  • The phase lead coil to match the new burden. The lead is set by the ratio L/R. Drop R and you must drop L with it. These two go together or not at all.
  • Bleeder resistors on the buck's output. Without them the ramp does not come back down, because a buck can only add charge. Mandatory.
  • An amplitude limit, so the bridge is not taken past its voltage. Worth having, and it is not protection: if the buck's switch fails short the bridge gets the full bus regardless of what the firmware thinks.

Three ways to hold it, and why this page is about the third

  • A damper, R+L+C across the primary capacitor, which suppresses the lower pole. Passive, does not touch the driver, has to be tuned in place.
  • Primary tuned slightly above the secondary, so the driver settles up there on its own. Free, and it puts the pole rather high.
  • A starting oscillator or a PLL, which forces it regardless of Q. The cleanest, and it means changing the driver.

A PLL is usually a 74HC4046 with the VCO centred on the upper pole and the capture window trimmed so the lower pole is not inside it. Then there is nowhere to fall to. Two things to watch: capture time at the start of the bang, which wants the VCO pre-biased, and loss of lock when the arc strikes ground, where an XOR phase detector is the more robust choice.

Self-oscillation, from the people who did it

The recipe came out of Mathieu thm's build thread and was confirmed by davekni:

Mathieu thm: removed R7, put a 50k resistor between pins 3 and 7 of the TL3116, and changed C33 for a 300 pF one. davekni: looks ideal, and recommends staying with self-oscillation.

What is happening there. The comparator's hysteresis feedback runs in two parallel branches, a DC one through R7 at 100 kΩ and a pulse one through R26 and C33. Removing R7 and running a resistor from the output back to the signal input turns the comparator into an oscillator: it starts swinging on its own instead of waiting for the current transformer.

The capacitor sets the frequency, roughly:

f [kHz] ~ 139000 / C [pF]

And put it slightly above that pole rather than on it, which is the part usually left out and is not specific to any one coil:

lower pole < upper pole < self-osc

Set that way, the pole you want sits between the oscillator and the pole you do not, and has to be crossed to reach it — the upper pole becomes a fence. Set the oscillator below the upper pole and both poles are on the same side of it, with nothing in between.

The capacitor is what sets it, and on one machine the difference between two neighbouring values is the difference between a fence and no fence:

poles at 317 and 519

250 pF -> 556 kHz
  317 < 519 < 556   fence
270 pF -> 515 kHz
  317 < 515 < 519   no fence

Interactive: the driver's free-running frequency against the two poles of the coil. Set above the upper pole, the upper pole stands between the oscillator and the lower one. Set below it, both poles lie on the same side and the guard is gone.

Frequency axis showing lower pole, upper pole and the self-oscillation
C11
250 pF
Self-oscillation
556 kHz
Gap to the upper pole
+37 kHz
Upper pole excited more by
23.6 dB
What the barrier is. The driver free-runs at whatever C11 sets, and the tank answers loudest at whichever pole is nearest. When the free-running frequency sits above the upper pole, the upper pole lies between it and the lower one: to reach the lower pole the system would have to pass through a stable operating point, and it does not. Drop the frequency below the upper pole and that geometry is gone — the oscillator is now between the two, with a pole on each side.

Twenty picofarads decide it. 250 pF puts the oscillator outside the pair; 270 pF puts it between them. The reading that 515 kHz is "close enough" to 519 gets it backwards: closeness is what makes it useless, because the work is done by the sign of the gap, not its size.

And it holds for the whole ramp. The upper pole falls from 519 to 463 kHz as the arc grows while C11 holds the oscillator still, so the gap only widens. The barrier is never weaker later than it is at the start.

Derived. Poles 317.0 and 519.1 kHz from f_pri 349.9, f_sec 426.49 and k 0.421, all JavaTC. Frequency from f [kHz] ≈ 139000 / C11 [pF], a model checked against one field result three per cent out. The excitation figure is each pole's response to a drive at the oscillator's frequency, off the unloaded peak sharpnesses — it says which mode the tank builds first, not how much power reaches the arc. Stray capacitance pulls the real frequency down, which is the direction that loses the barrier, so this is a number to measure on pin 7 with the bridge dead rather than to trust.

Twenty picofarads, and the oscillator moves from just outside the pair to between them. At that frequency there is nothing for the upper pole to protect: the driver is already on the wrong side of it and the lower pole is downhill all the way. That is the whole argument for the smaller value, and reading it as "515 is close enough to 519" gets it exactly backwards — being close is what makes it useless, because the sign of the gap is what does the work.

Two smaller notes from the same work: it only functions with the phase lead network in circuit, because otherwise the loop does not close properly; and a 1N4148 is preferable to a Schottky in that path, because more voltage on the node makes for cleaner oscillation.

Which protection mode, and the word that means two things

A UD2.9X offers both, and the manual's own wording decides it. Ordinary OCD: the pulse ends and goes back to steady state until the next interrupter pulse. Pulse skip: it drops a single oscillation without killing the pulse completely.

On a DRSSTC pulse skip is the kinder of the two — losing one cycle out of a few hundred microseconds costs nothing and the bang survives. On a ramp the arithmetic inverts. "Until the next interrupter pulse" is until the next bang, so ordinary OCD gives a clean, predictable end to the ramp. Pulse skip keeps the burst running through whatever caused the trip — and if that was the driver losing the upper pole, the bang finishes on the lower one, which is the mode the machine was not built for.

So start with ordinary OCD and add pulse skip afterwards, if at all. The board and its wording are WaskaLabs' UD2.9X.

Be careful with the designators

The good news is the other face of the same fact. The comparator core did not change from UD2.1 through 2.5 to 2.7; Ward wrote that the main logic and drive circuits are unchanged. So the recipe transfers legitimately between revisions and onto clones. What transfers is the logic, not the part numbers.

The one that is not on the list

Nothing above turns a DRSSTC into a QCW by itself, because the buck is not in the driver. The modulator is a separate converter with its own switch, its own choke and its own gate supply, and it is the department in one part.


Why the upper pole has to be forced at all, rather than preferred, is on the ramp's frequency page: with plain feedback this coil settles on the lower pole at both ends of a bang, so the changes below are the difference between the machine working and not.

The QCW diagram labels its driver "driver and lead" for the reason in the second bullet, and gives the modulator a line of its own running up the outside to the buck.

more in QCW