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The UD DRSSTC driver boards: which revision you are holding

The logic core did not change from 2.1 to 2.7, so modifications transfer between revisions. The part designators do not, and that is what wrecks a repair.

CommonGnd4 August 202619 min read

Steve Ward's Universal DRSSTC Driver is the board the rest of the field is described against, directly, through a clone, or through a rebuild that is explained by how it differs. Knowing which revision you are holding matters, because the logic travels between them and the part designators do not always travel with it.

What it is and why

One board doing the four driver jobs. It finds the coil's frequency, from a current transformer through a comparator. It advances the switching instant, with a phase lead made of a series L + R in place of a bare burden resistor. It decides when to stop, on the interrupter's enable or on current. And it delivers charge into the gates, through an output stage into a gate drive transformer.

On the UD2.x boards the first and third of those get a current transformer each, one ring for feedback and a separate one for protection, which is two rings, not one. The UD3 puts both jobs on a single input by design, and that page carries what the sharing costs. So the two rings are a property of the analogue boards, not of the line.

The reason the family is worth knowing as a line rather than as a product is that the comparator and flip-flop core did not change through 2.1, 2.5 and 2.7. Gao Guangyan's change list from UD2.0 to UD2.7A is regulators, layout, solder pads, board size and an under-voltage lockout, and he says the earlier work by others was small fixes, an extra fibre input and component placing (loneoceans). A modification published against one revision therefore transfers legitimately to another. Two members of the list are outside that: the UD+ replaces the discrete logic with a CPLD and the UD3 replaces it with a processor.

The revisions

UD1.3b, Ward's own, published on his site in 2008 with schematic, board files and a parts list. Primary current feedback, a flip-flop, an optical interrupter input, overcurrent detection and a MOSFET-driven gate drive transformer output, and no phase lead.
UD2, Ward again, adding adjustable lead compensation through a variable inductor. loneoceans credits the idea of adding lead to the feedback signal to Finn Hammer, who called it the Prediktor.
UD2.1b, from Phillip Slawinski and Bart Anderson. Ward's own published design files stop at the UD2.1 revB schematic of March 2011, which is where the phase lead page takes his bill of materials from.
UD2.5, from Eric Goodchild. It added the Industrial Fiber Optics receiver alongside the ST one, a test point for the overcurrent detector, and error fixes. Two independent pages name him: loneoceans in the history section above, and Daniel Marks in the DRSSTC PCB Pack README.
UD2.7, Gao Guangyan's revision of Ward's UD2, published with Ward's permission and with all rights to the UD2 design left with Ward. Rev A and B are from September and October 2014, Rev C from January 2015. The switching 9 V regulator, the under-voltage lockout and the smaller board are his; so is the change of lead inductor family, from the Coilcraft Slot Ten parts in Ward's revB bill of materials to the Coilcraft Slot Seven 7M3 series. He gives the tested frequency range as 12 kHz to 1 MHz. He also publishes the schematic of every revision, A, B and C, alongside gerbers and a bill of materials, on his own page; go there rather than to any copy, because the terms he sets are download for personal hobby use and nothing broader.
UD2.8A, Daniel Kramnik's revision of the UD2.7, in his own words a slight one: a jumper to pick between the two fibre inputs, SMA connectors instead of Molex, a barrel jack, surface-mount indicator LEDs and a relayout. The lead stays a tunable inductor, as on the board it revises.
UD2.9, Daniel Marks' through-hole rebuild of the UD2.7C with a pulse skip jumper, in the DRSSTC PCB Pack, Kicad sources under CC-BY-SA. It keeps the 51 Ω feedback burden, the 5.1 Ω overcurrent burden, the Slot Seven 7M3 lead inductor and both fibre receivers. What it does not keep is the numbering, and that is the next section.
UD29X, from WaskaLabs. Its README describes it as a standard surface-mount UD like the UD2.7C with differences: pulse skip inspired by Marks' UD2.9, the under-voltage lockout set by a fixed resistor instead of a trim pot, a single ST receiver instead of the ST and Industrial Fiber pair, 24 V DC input only, one gate drive channel, and breakout headers for extensions.
UD+, Phillip Slawinski's. Freewheeling: over current it turns one half bridge off and lets the current circulate rather than cutting the bang. The deeper change is that the 74-series logic is replaced by one CPLD written in VHDL, with the sources published. Its lead inductor is not fixed by the line either: the board takes Slot Ten or Slot Seven parts, and the working combinations Slawinski lists for CM600 and CM300 modules are Slot Ten.
UD3, Jens Kerrinnes' programmable driver, built on Ward's work and published as Netzpfuscher/UD3. Interrupter on board, a command line, USB-MIDI, autotuning, telemetry, master and slave. This is where the line gives up the inductor and sets the lead as a time instead of an angle, in nanoseconds. It is a different kind of board from the ten above it, and what it ships set to is read out of its own source rather than documented here.
Eastern Voltage Research's Universal DRSSTC Controller is not a revision in this line at all. It is a product sold alongside it, in a shielded enclosure, with two current sense inputs for 1000:1 transformers, coarse and fine overcurrent knobs, and it supplies the lead as socketed plug-in inductor modules, IND-1 to IND-8, chosen by the size of the switch (datasheet, March 2014 Rev 1). Note what the modules are not. Each is a range, IND-1 at 9 to 15 µH up to IND-8 at 60 to 100 µH, so the part is still tuned after it is plugged in; and IND-1's 9 to 15 µH is the same span loneoceans gives for the Coilcraft 7M3-123. What changes is that the inductor is socketed instead of soldered.

One of the eleven, with its silkscreen readable

One revision in that list comes with board artwork published under a licence that permits reuse, and it is the one the rest of this page is written against.

Bare board render of the UD2.7C through-hole driver, silkscreened UD2.7C THRU-HOLE. Down the left edge, connectors labelled 24 VAC, +24 VDC minus, Feedback, Lead Inductor, SLOT 7, OCD and POWER. Down the right, the gate transformer header and four MOSFETs, two IRF9540 and two IRF540. Across the middle, LT1016, LM311, 74HC08, 74HC74, 74HC14 and a UCC27425, with an OPF2412T and an IFD95T fibre receiver at the bottom left. — Board layout by Daniel L. Marks, 2018, CC BY-SA 4.0, from the DRSSTC PCB Pack.

What the render shows that the list cannot. The left edge is the argument of two other pages, printed onto the board: Feedback and OCD are separate connectors, because they are separate transformers, which is two rings, not one. Lead Inductor and SLOT 7 are silkscreened on, which is what it means for a revision to fix the lead as a part rather than as a number, and what the UD3 gave up.

The UD2.9 board is this one with a group of parts added in the lower right corner and a thermal disable header beside them, which is why its render is not printed here as well: at this size the two are the same picture. The difference is legible on the schematics below, where it has net names on it.

The schematics themselves

The same pack publishes the circuit, not only the board, and under the same licence. These are the drawings the section below is read from.

Full schematic of the UD2.7C through-hole driver. Top left, the supply: a bridge rectifier into LM7824, LM7812 and LM7805 regulators. Left of centre, the feedback input at J3 through a 150 pF and 100k network into a TL3116 comparator, with the lead inductor at J4 and L1 in the Slot Seven position and a note reading that if phase lead is not used J4 must be shorted. Bottom left, the two fibre receivers OPF2412T and OP2 IFD95 into 74HC14 inverters, and the overcurrent input at J5 through 1N5818 clamps into an LM311. Centre, 74HC08 and 74HC74 logic. Right, a UCC27243 driving four MOSFETs, two IRF9540N and two IRF540N, into the gate transformer header at J8. The title block reads UD2.7C Through Hole, drafted by Daniel Marks, February 8 2018. — UD2.7C. Schematic by Daniel L. Marks, 2018, CC BY-SA 4.0, from the DRSSTC PCB Pack. Open it full size to read the designators.

Full schematic of the UD2.9. The supply, feedback front end, fibre receivers, overcurrent comparator and gate output stage are the same as the UD2.7C. What is added is a group at the lower right carrying named nets INTERRUPTER, INTERRUPTEREDGE and UNDERVOLT, a 2N3906 transistor Q5 with resistors R23, R25, R28, R29 and R30, further diodes, and a two-pin header J16 labelled close for skip pulse. The title block reads Universal Driver Modified to include Skip Pulse, UD2.9 Skip Pulse, drafted by Daniel Marks, February 28 2018. — UD2.9. Schematic by Daniel L. Marks, 2018, CC BY-SA 4.0, from the same pack.

Set the two title blocks beside each other and you get the size of a revision in this line. 8 February 2018 and 28 February 2018, the same hand, twenty days apart. Everything up to the gate output is the same drawing. What is new is a handful of parts around a transistor and a header marked close for skip pulse, and on the board it is the group sitting in the lower right corner. What the added circuit is for, and why a QCW wants the other setting, is with the driver conversion.

The same pack has a third drawing, and it is what this line looks like once it leaves the analogue core. Marks also published a through-hole board for the UD3 idea, its title block reading Universal DRSSTC Driver ver 3 for CY8CKIT-059 and dated 1 April 2018, credited in the pack's own notes to Steve Ward and Jens Kerrinnes. It is not Kerrinnes' board, which is Altium sources carrying no licence. It is a third party's build of the same idea, drawn by the same hand that drew the two above, which is exactly what makes it readable beside them.

Full schematic of a through-hole Universal Driver 3 built around a CY8CKIT-059 PSoC5 development board. The dev board occupies the lower left with its pins broken out down both edges. Top left, the supply: L7812, L7805 and a TC7660S charge pump for a negative rail. Top centre, the single current transformer input at J6 with a 3R3 burden resistor R7, clamped by a 1N4733A and four 1N5819 diodes, from which three signals are taken: ZCDA and ZCDB through 100R resistors and 150 pF capacitors, and CTout through a 1k resistor and 150 pF. Centre, two TL082 op-amps at U7 turning the J7 input into Vbus and VIn, and an Ibus chain from J8 through 49R9 and 470R. Lower centre, thermistor inputs Therm1 and Therm2 at J2 through 100R resistors. Right, two UCC27423 gate drivers, each feeding four MOSFETs, two IRF9540N and two IRF540N, into a gate transformer header through a 1 microfarad capacitor and a 15R resistor, at J4 and again at J5. Bottom right, a 2N7000 and fibre transmit and receive lines at J13. The title block reads drafted by Daniel Marks, version April 1 2018. — Universal DRSSTC Driver ver 3 for CY8CKIT-059. Schematic by Daniel L. Marks, 2018, CC BY-SA 4.0, from the same pack. Open it full size to read the designators.

Three things are gone and three are new, and both lists are short enough to hold in your head.

Gone: the comparator, the flip-flop and the lead inductor. No TL3116, no 74HC74, no Slot Seven position on the board. A dev board sits in the middle of the sheet and every decision the two drawings above make in hardware has moved inside it.

New, and this is the one to carry: one ring input, three signals off it. J6 is the only current transformer connector on the board. Its burden is R7, 3R3, clamped by a 1N4733A and four 1N5819s. From that single node the sheet takes ZCDA and ZCDB through 100R and 150 pF, and CTout through 1k and 150 pF, and lands them on three separate pins of the dev board, B8, B7 and B6. So the thing this site keeps arguing with is not an economy somebody made at the bench. It is one connector, one burden and a fan-out, drawn that way on purpose, and what the sharing costs is two rings, not one.

New: it measures three things no UD2 measures. Therm1 and Therm2 arrive at J2 through 100R and 0.1 µF. A pair of TL082s at U7 turn J7 into Vbus and VIn. An Ibus chain runs from J8 through 49R9 and 470R into a 1 nF. The analogue boards know the primary current and nothing else about the machine. This one knows its own temperature, its bus voltage and its bus current, which is what autotuning and telemetry are made of and also why its settings live somewhere the silkscreen cannot tell you about.

New: the gate output is doubled. The UD2.7C drives one header. This board has the same output topology, four MOSFETs into a gate transformer through a series capacitor and resistor, built twice, at J4 and at J5.

And what goes to each of those terminals

The silkscreen names the connector and not what belongs on the end of it. Read the render at the top of this section against the schematic under it, and the whole board comes to nine terminals and two of them are only indicators.

Three of those are the ones the rest of this site spends pages on:

Feedback and OCD are different holes. Two rings, two burdens, two jobs, and the reason is two rings, not one. A board that gave you one hole would be making the decision for you.
Lead Inductor is a hole at all, which is the whole of what this line did until the UD3 stopped doing it. The schematic carries the instruction the silkscreen cannot: "If phase lead is not used, J4 must be shorted." Leave it open and nothing works, and nothing tells you why.
Gate Xformer is the only thing the board drives. Everything else on the edge is an input or a lamp. What the driver actually decides is worked inside the driver.

What will get you

Part designators move between rebuilds, and the same component by function is called different things. The feedback burden is R1 on Ward's UD2.1 revB and on the UD2.7C bill of materials, and R3 on Marks' UD2.9. The overcurrent burden is R17 on the UD2.7C and R11 on the UD2.9. C33 is the dead time capacitor on the UD2.7C, is called C22 on the UD29X by that board's own README, and on Marks' UD2.9 C33 is a 2.2 µF ceramic disc, a different part entirely. Identify by function and by continuity, never by the silkscreen in somebody else's photograph.

A phase lead value copied from another board's thread is only a value against that board's burden resistor. The network sets the ratio L/R, so an inductance quoted in a UD2.7 thread carries the 51 Ω with it silently. The phase lead page works the whole chain, including what happens when the burden comes down.

Removing the L+R section is not a simplification, and the board can show you so. The UD2.7 has a three pin header beside the inductor that selects R alone or R and L together. loneoceans scoped both on his own DRSSTC at about 380 kHz with the bridge at about 170 V of bus: with the lead jumpered out the collector to emitter transitions carry spikes he measures as "greater than 100V", and he says these can kill IGBTs because they are extremely sensitive to over-voltage. With a suitable inductor fitted and tuned, the spikes fall away.

The numbers

Feedback burden: 51 Ω, 2 W. It is R1 on Ward's UD2.1 revB and on the UD2.7C bill of materials, and R3 on Marks' UD2.9. C32 is a 150 pF across it on the UD2.7C, and R2, the resistor that carries the signal on into the diode clamp before the comparator, is 1 k.
Overcurrent burden: 5.1 Ω on the same boards, with a second parallel pad provided for large machines. R17 and R28 on the UD2.7C, R11 and R12 on the UD2.9.
Volts across that 51 Ω: loneoceans states the phase lead circuit runs a deliberately high voltage across the network, "~50+V across the 51R at 1A", and gives the reason: the comparator's delay from zero crossing to output is smallest when the signal arriving is large, which matters most in the first cycles of a bang. See the note below, because a live page reasons the other way from the same pair of figures.
Lead inductor family: Coilcraft Slot Ten in Ward's UD2.1 revB bill of materials; Coilcraft Slot Seven 7M3 on the UD2.7 and on Marks' UD2.9; and either family on the UD+.
The ceiling on an L+R lead: a quarter of a period, because arctan cannot exceed a right angle. Across the UD2.7's own tested band that is 20.8 µs at 12 kHz and 250 ns at 1 MHz [derived, the quarter period at the two ends of loneoceans' tested 12 kHz to 1 MHz]. That ceiling is what the line eventually runs into, and it is the numeric reason the last board in the line sets a time rather than an angle: above those frequencies no inductor buys the lead the wiki asks for, whatever it costs.

One correction to a figure this page used to carry, and one to a live page. The 1000 to 2000 ns this page previously gave for a large brick had no source, and it is withdrawn in favour of the UD3 wiki's 500 and 1000, because the wiki is the document and this page's figure was not read out of anything. With the withdrawal there is no second party to that disagreement left, and the wiki's 500 and 1000 stand on their own. In the other direction, the phase lead page briefly reasoned that an ampere into the 51 Ω feedback part was impossible because it makes 51 V. On this board that is exactly what the designer does, on purpose, and he gives the reason on the page above. That has since been corrected there, and one step of its arithmetic is worth keeping in view anyway: a 2 W part rating does not cap the peak current through a burden on a machine that runs bangs rather than a continuous sine. It caps the average, and the average is set by your on time and bang rate rather than by the board.

What is not established

Whether any clone substitutes ordinary signal diodes for the Schottky pair that squares the feedback. Both open boards fit Schottky there: MBR0530 at D1 and D2 on the UD2.7C bill of materials, 1N5818 or 1N5819 on Marks' UD2.9, with 1N4148 parts used elsewhere on both boards. Every bang starts open loop points at this page for the claim that a clone's changed feedback diodes are why it will not start on copied settings. This page cannot support it: no clone schematic has been read here, and the mechanism is not obvious either, since below a diode drop the clamp is not conducting and both boards behave alike.
Which board the Chinese clones actually derive from. Two open branches exist, Marks' pack and WaskaLabs' UD29X, and the UD2.7C is documented at length on loneoceans, which is where the UD29X README sends its own readers for the theory. Nothing read here settles which of the three any particular clone was traced from, and this page previously named the UD29X without a source.

What goes wrong

A modification does not fit the board. The designators moved; the logic did not. Trace the function.
Hard switching after a "cleanup" rebuild. The L+R section was left out, or the header beside the inductor is selecting R alone.
The lead is right at one frequency and wrong at another. An L+R network holds an angle, and the hardware needs a time. On a wide sweep that is the technique running out, not a component fault, and it is the reason the UD3 states the lead in nanoseconds.
A setting copied from another revision's thread does nothing you expected. Burden and inductor go together. Check which resistor the thread's board had before trusting its inductance.

Where next

Inside the driver, what the board is doing and why.
DRSSTC phase lead: what it is made of, which inductor to fit, and the inductor is the part these revisions keep changing.

Attribution: the revision history, the change lists and the UD2.7 figures are Gao Guangyan's, on loneoceans and in his bill of materials; the UD1.3b files are Steve Ward's; the UD2.9 board and its bill of materials are Daniel Marks', as are the UD2.7C through-hole rebuild and the CY8CKIT-059 board whose schematic is printed above; the UD29X is WaskaLabs'; the UD+ is Phillip Slawinski's; the UD3 firmware and wiki are Jens Kerrinnes', building on Ward. The quarter period ceiling and the four figures derived from it are ours, and are marked where they appear.

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