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Inside an SSTC driver: feedback, phase lead and protection

The network holds a constant angle while the hardware needs a constant time. That mismatch is the limit of the whole technique, and a QCW walks straight into it.

CommonGnd4 August 202611 min read

The driver board holds all the logic: the feedback, the phase lead, the interrupter, the current protection and the output stage that reaches the gates. Without it the power section is a bridge and nothing else.

What it is and why

feedback CT -> burden -> COMPARATOR -> logic -> output -> GDT -> gates
                             ^
protection CT -> burden -> OCD comparator      interrupter -> ENABLE

Four jobs on one board. It finds the coil's frequency, because that frequency is not a number you can set once. It advances the switching instant, because by the time a signal has crossed the board the current has moved on. It decides when to stop, on current or on the interrupter. And it delivers enough charge into the gates to make the transitions fast.

Three of those four are settled on the board, and everything below is one of them going wrong. The fourth is settled past the board's edge, in the gate transformer and the loop behind it, and the only part of it that is here is what holds a gate down when the drive is absent or wrong.

What you decide

A comparator, not a Schmitt trigger

Criterion: whether the threshold has to be predictable. For feedback and for current protection it does.

Do not use a 74HC14. A logic trigger's thresholds move with temperature and supply voltage, and both jobs need a threshold you can predict. Use a real comparator, and put its propagation delay into the lead budget alongside the driver's and the GDT's.

How much phase lead, and how to make it

The switching has to happen before the current zero rather than on it, and the classic implementation is a series L + R in place of a bare burden resistor:

phi = arctan(w·L / R)

The lead is set by the ratio L/R, not by the inductance. Reduce the burden and you must reduce the coil in proportion, or the angle moves.

There is a mismatch built into the idea. The network holds a constant angle while the hardware needs a constant time: the driver's delays are fixed nanoseconds, and the same angle at different frequencies is a different number of them. That is the limit of the technique across a wide sweep, and it is exactly what a QCW does to itself as the arc grows.

What the lead is made of, how much of it is the ZVS floor rather than the delay chain, and which inductor delivers it, is its own piece.

Why the feedback comes off the primary at all

This is usually presented as a design choice. It was a fix for a specific failure that was destroying hardware: under a ground strike the secondary stops ringing at its own resonance, so a driver following it switches at the wrong instants into a full bus. Steve Ward says so in his own log book and names it as the reason he moved to primary current feedback, and the strike itself, with his words and the four other things it does, is what a ground strike does to a DRSSTC.

Taking the feedback off the primary current makes the loop deaf to what the secondary does under a strike. The whole UD line rests on that conclusion, and the reason for it is rarely stated.

The overcurrent detector arrived in the same stroke and for the same adversary, which is why the two are usually found together. The strike itself does three more things besides, and they are on one page.

How strong the feedback is

Criterion: volts per amp of primary current, not how many turns the transformer has.

feedback strength = |Z| / N,   clamping at I = V_f · N / |Z|

Working implementations sit around 0.02 to 0.04 V/A. Three or four times that and the signal reaches the clamping diodes almost immediately, which is the failure in the next section.

One published build sits four times above that band and works. Gao's QCW lists its feedback transformer as "300 turns with 47 Ohm giving 0.157V/A", and the arithmetic closes exactly (loneoceans). That is at the top of the "three or four times" the sentence above calls a failure, on a coil that made metre arcs. Which means one of two things and this page does not establish either: the band is narrower than practice, or clamping early is not a failure on a driver that only wants the zero crossing out of the signal. And there is a third reading that decides the value before either of them does: 47 Ω is a DRSSTC number. A QCW has two poles and walks between them every ramp, and the transformer's own phase error grows as one over frequency squared, so a large burden hands the lower pole the most help exactly where it is least wanted. That argument, and what it costs at each rung, is at the transformer. Size the burden for the machine class first and read the band second. The transformer end of this is

two rings, not one.

What the protection does when it fires

Two behaviours, and they suit different machines. OCD ends the bang and waits for the interrupter. Pulse skip drops one cycle and lets the bang continue, which is what a long bang wants.

Either way it needs its own current transformer. A shared one, loaded by the phase lead network, saturates its core and the protection weakens exactly when it is needed. It can also be slow, a few cycles, so the threshold sits below the destructive current rather than at it. Overcurrent is not a setting is the whole argument.

What holds the gate down when the drive is not there

Three cases, and they need three different answers, which is why they get confused with each other.

The driver is putting out nothing at all, during start-up, if its supply fails, or if a wire comes off the transformer. A pull-down from gate to emitter, tens of kilohms, holds the device shut. Cheap, and the failure it prevents is the expensive kind.
The driver is putting out rubbish rather than silence, which is the sagging supply case below. A pull-down cannot help here, because the drive is real and it is wrong. This is UVLO's job and nothing else's.
The driver is doing exactly what it should, and the gate is being lifted by dV/dt from the other device through C_gc. Neither of the above touches this one.

A pull-down is not dV/dt protection, and treating it as such is how people get caught. Shorting a gate to its emitter through tens of kilohms does not hold it down against a fast edge on the switching node. Real immunity is an active Miller clamp, or a gate loop short enough not to need one, and the loop is the transformer's construction problem.

A gate-to-emitter TVS is secondary insurance rather than the answer. It belongs directly on the gate pin, bypassing the gate resistor, and the common choice is wrong. Measure it against a real gate. An FGA60N65SMD is rated VGES ±20 V, with a transient gate to emitter rating of ±30 (onsemi datasheet). A P6KE27CA stands off 23.10 V and does not break down below 25.70 (Yageo P6KE series), so at that ±20 V limit it is still an open circuit and it protects nothing. An SMBJ16CA is the better part: 16.0 V stand-off, breaking down between 17.80 and 19.70, which is inside the limit (Yageo SMBJ series). But read the rest of its line before believing in it. Its clamping voltage at the full rated surge, 26.0 V at 23.1 A on a 10/1000 µs pulse, is well above the gate's 20 and under its transient 30. So it holds the small stuff below the steady limit and merely holds the big stuff to something the gate survives. Insurance, not protection, and that distinction is the whole reason it does not replace a short gate loop.

What will get you

Barnkob's UD3 bring-up counts that rule out on a full bridge: three differential probes and one ordinary. Both accounts are with the scope.

And the three grounds are three different things: the high side's floating ground, the low side's fixed ground, and logic ground. Logic joins power at one star point, so that power currents have no path through the logic.

The numbers

Feedback strength on working boards: 0.02 to 0.04 V/A.
Burden resistors on a UD board: feedback 51 Ω 2 W, overcurrent 5.1 Ω 0.5 W. The wattage tells you what current the author was designing for.
Delay chain on the reference bridge: about 184 ns, of which 115 is the switch itself. A datasheet sum, not a measurement.
Where lead angles stop paying: 45 to 60 degrees. Diminishing returns rather than a physical limit, because the amplitude across L+R grows as |Z|/R while the useful in-phase part goes as cos φ, and 90 would take infinite inductance.

What goes wrong

The frequency wanders, or the coil will not start. Feedback. Check the winding direction of the transformer first: turning the ring over is the test.
It runs beautifully at low power and badly at high. Clamping. The signal is clipped above some current and the driver is no longer tracking anything.
The protection never fires, or fires on every bang. The threshold, not the knob, and possibly a shared transformer saturating.
Both devices in a leg die when the supply is marginal. No UVLO, or UVLO without hysteresis.
A board that worked stops the moment a probe touches it. The probe ground went somewhere that is not the driver's ground.

Where next

The UD boards, the line every other driver is described against, and what changed between revisions.
What a phase lead actually buys.
Overcurrent is not a setting.
The gate loop is an RLC, where the fourth job finishes. The gate resistor, the diode across it and the local turn-off are all on that page rather than this one.

The driver is a box on all three department diagrams, with the gate transformer above it and the current transformers feeding it from the right.

driverfeedbackUD