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QCW gate supply for long bangs: amps and millifarads

On a DRSSTC it is a detail. On a QCW it is amps of average current and millifarads of capacitance, and a factor of four here is a dead bridge.

CommonGnd4 August 202610 min read

On an ordinary DRSSTC the gate supply is a detail. On a QCW it is not, and this is where people get it wrong repeatedly.

The reason is the length of the bang. The bridge switches for ten to twenty five milliseconds without a break, not for a few hundred microseconds. The charge accumulates.

Q per ramp = Q_g × (devices) × (transitions per cycle) × f_working × t_ramp

The three factors people leave out

Count the charge over the full swing. On a bipolar ±24 V supply the gate travels from −24 to +24, not from 0 to 24. The datasheet's Q_g is quoted for a stated swing and has to be scaled to yours.
Both devices in a leg. While the supply is charging one gate from −24 to +24, it is discharging the other from +24 to −24.
Twice per cycle, not once.

The order of magnitude

For a bridge device at about 400 nC over the full swing, running at 400 kHz with a 25 ms ramp. The 400 nC is davekni's, an FGH75T65SHD's gate charge extrapolated to ±24 V in that thread, and the 400 kHz and the 25 ms are his assumed figures too. Note the part is a smaller one than the buck's own switch, and the brick is on the record rather than estimated: the reference build's buck switch is an FF300R12KS4, which Gao names with its charge beside it, "3200nC gate charge" (loneoceans), and Infineon's own datasheet for that module gives QG = 3.20 µC at VGE = -15 V to +15 V. So the bridge device carries about an eighth of the brick's charge [derived, 400 nC against 3200], and it carries it across a wider swing than the brick's figure was measured on.

That swing is past the part's rating, so read the budget below as a ceiling. The FGH75T65SHD's absolute maximum |V_GE| is 20 V, with 15 V as the operating figure on its data sheet, and ±24 V is a 48 V swing against a 40 V limit. Nobody is proposing to build that: the extrapolation is a way of getting a charge, not a drive. But every figure in the two lines below is proportional to it, so at the rated ±20 V they come down to about 83 per cent and at the ordinary ±15 to about 62 [derived, by swing]. Those two are themselves upper bounds on the reduction, because the Miller plateau is a fixed part of the charge and does not shrink with the rails. What the arithmetic is for is the order of magnitude and the shape of the demand, and both survive the factor. Two devices, so a half bridge or one leg of a full one:

counting only the charging of both gates: 8 mC per ramp, 0.32 A average, 4 mF for a 2 V sag;
counting charging and discharging: 16 mC, 0.64 A, 8 mF.

And what a rail that sags actually does

The arithmetic above stops at a number of farads, which makes it look like a component-selection problem. It is not. Follow it one step further and it turns into the failure people actually see.

dV = Q / C

Take one leg's 16 mC and put it against a reservoir chosen for a different job. At 4 mF that is a 4 V droop over the ramp; at 1 mF it is 16, and both double for a full bridge. The gate rail does not fall off a cliff, it sinks steadily for twenty five milliseconds.

And nothing about that is gentle when it arrives, because the driver is watching that rail. UVLO sits a few volts below the nominal, so a supply sagging by more than that does not degrade the edges, it switches the driver off part of the way through the bang, and it does so mid-ramp, at the point where the arc is longest and the bus is highest. The bridge stops driving while the tank is still full.

The reservoir sizing above is therefore not "enough to keep the edges pretty". It is enough that the droop stays under the UVLO's margin for the length of the longest ramp you intend to fire, which is a different and larger number, and it is the one to design to.

Local beats large

A local electrolytic, something like 470 µF, plus a fast ceramic bypass right at the pins, delivers current before the supply cable's inductance has time to notice. A big bank at a distance does not save you, because the cable is in the way.

What that means on the board in front of you

Everything above is a charge and a droop with no part number in it, and the part number is where it stops being arithmetic. Take the driver most of these coils are built on. Gao Guangyan documents the UD2.7's own supply on his page: the reservoir is the pair C4A and C4B, "the default values for C4A/B at 8mm diameter 35VDC 220uF capacitors", with a third position, C4C, added on the Rev B and C boards, and the board wants "19 to 26.5VAC recommended input, with 18-28VAC absolute limits" or a 24 V DC supply. On how much is enough he does not give a rule, he gives an instruction: "a roughly 30VA power source should be sufficient for most coils, but you should calculate the total gate drive power required to be sure." Calculating it is what this page is.

So calculate it. Four hundred and forty microfarads against the charge from the section above, on a 24 V rail:

                          one leg      full bridge      [derived, Q/C]
C4A + C4B, 440 uF          36.4 V          72.7 V
  at the rated +-15 V      22.5 V          45.1 V

That is not a droop, it is the rail leaving. Which is the right answer for the machine the board was drawn for: a DRSSTC bang is over in a few hundred microseconds and 440 µF is generous for it. The same board on a twenty five millisecond ramp is a different question, and the numbers say so before anything smells hot.

And he answers it himself, on the same page, for exactly this case. "Add extra bus capacitance on the 24V rail... I found adding an extra 1000-5600uF capacitor works great depending on your application", together with "use a 24V switch mode power supply as a power source (instead of a 20V transformer)". Take the top of his range:

440 uF + 5600 uF = 6.04 mF   one leg 2.6 V   full bridge 5.3 V
  at the rated +-15 V                1.6 V               3.3 V

Read what he did there against the two branches above, because it settles which one a board maker actually takes. Six millifarads is 38 per cent of the 16 mF this page's own column asks for [derived], and that column's condition is that the supply hands over nothing while the ramp runs. He does not meet it. He changes the supply instead, from a transformer to a switch mode unit, which is the current branch, and then fits enough capacitance to cover the cable and the gaps rather than the whole ramp. That is the same choice the note above asks you to make, made by the person who drew the board.

And the buck's own switch

The buck's gate supply has two separate traps of its own, and both are quiet killers.

There is a third, at the switching frequency: the average gate current is Q_g · f and grows linearly, so how soon a module runs out depends on which rail it is driving. On that 3.20 µC brick and a symmetrical ±15 V, a two watt isolated module is spent at about 21 kHz, and 60 kHz asks 5.76 W, which a five watt module no longer covers; on a single +15/0 rail the same switch does not reach two watts until about 42 [derived, Q_g · f · swing, all three]. Do not carry the ±24 V of the bridge above into that sum. The rows, the asymmetric rail between those two and the reason to read all of them as ceilings rather than values are with the choke, because that is where the hidden price of the frequency knob is paid.

The gate transformer on the QCW diagram has the driver coming up into it from below and the gates coming down from above, and this is what has to be behind the driver's own supply pin for a ramp that lasts twenty five milliseconds.

gate drivesupplyQCW