A gate drive transformer is a small ferrite ring with a few turns on it, wired between the driver and the bridge. You need one because the top devices in a Tesla coil bridge have their emitters on a node that swings by hundreds of volts.
What a gate drive transformer is, and why the signal goes across magnetically
In a bridge, the bottom transistors have their emitters connected to the negative rail, which stays put. You can drive their gates from logic that shares that ground.
The top ones do not. Their emitters are connected to the output node, which swings from the bottom rail to the top rail hundreds of thousands of times a second. A gate has to be driven relative to its own emitter, so driving the top devices means driving something that is moving by hundreds of volts.
You cannot wire logic to that, so the signal goes across magnetically: one winding on the driver's side, one per device on the bridge's side, and no electrical connection between them.
A transformer is used rather than an opto-isolator because of speed. The edges have to arrive in well under 200 nanoseconds and they have to carry real current. A gate is a capacitor of several nanofarads, and turning the device on quickly means charging it quickly. A transformer does both without needing a power supply on the far side, which matters when the far side is floating.
What you decide: core, turns, wire and winding direction
Nearly every decision here is about construction, and each one shows up directly in the shape of the waveform at the gate.
The core
Two properties of the core matter. The "frequency range" line on a datasheet is not one of them.
Permeability sets the turns. Turns go as one over the square root of µ, so a core with half the permeability wants about forty per cent more of them.
Hot B_sat sets the saturation margin. Design against the hot figure, not the cold one on the front page. How much it falls by 100 °C depends on the material: a fifth to a quarter on the power ferrites, and past a third on the high permeability ones. The N30 example at the end of this article loses 37 per cent, from 0.38 T to 0.24. Both figures are TDK's own for the material, printed one under the other: BS (25 °C) 380 mT and BS (100 °C) 240 mT (SIFERRIT material N30), and the 37 per cent is the step between them [derived, 140/380]. Take it off the curve for the part you actually have.
Use an ungapped ferrite ring. Powdered iron is worse. The nanocrystalline alloys are better on both counts and cost accordingly. A gap costs you the magnetising inductance you need and gains you nothing here.
The catalogue's frequency range is a loss specification for power use at high flux density, not a ceiling, and a gate drive transformer swings a small fraction of that. Fair-Rite sell 77 as a broadband material good from 100 kHz to 10 MHz and wind 1.8 to 30 MHz baluns on it, while the power selector rates it "to 100 kHz". Both are true about different jobs.
What the number does tell you is where the permeability starts falling. Snoek's limit puts that at roughly 1500 to 2000 divided by µi, in megahertz:
f_rolloff [MHz] ~= K / mu_i
K = 1500...2000That is not a wall either. Past it µ declines gradually and the losses climb, but the part still works. The practical consequence is narrow: the effective A_L is below the low frequency catalogue figure, so the sag comes out worse than the arithmetic said.
This leads to a surprising result. At 460 kHz the cheap cores have more frequency margin than the good one, because their permeability is lower, and Snoek does not let you have both. N30 at µi 4300 rolls off at 349 to 465 kHz and is sitting on its own edge. PC40 and 77 have about twice the margin and want a third more turns for it. Winding a third more turns on a core with room is an easier trade than running on the edge of a high-µ one.
All of this assumes you know what the core is. Half the good ones on a coil came out of a dead switching supply with no marking, no datasheet and no A_L, and the turns calculation rests on A_L. It takes two minutes to find out.
Before you start unsoldering, know which part to take. The main transformer in a switching supply is almost always gapped, usually as a ground face on the centre limb, because the gap stops a flyback core saturating under its DC. A gapped core is the one thing a gate drive transformer cannot use. The part you want from that supply is the common-mode choke: a ring, ungapped, high permeability, wound as pairs, and built for much the same job. That is our reading of what those parts are for rather than a recommendation from a source, and the measurement below will confirm it or not.
There is one more criterion, and it comes from how a coil runs. The usual treatments of gate transformer saturation assume continuous operation. A coil runs in bursts, and a burst that ends anywhere other than at zero flux leaves the core sitting at its remanence B_r. The next burst then starts offset from the middle of the available swing, with the headroom in one direction short by that much.
Read the B_r line on the datasheet, because the materials differ on it by a factor of two. TDK's own table puts PC47 and PC90 at roughly 170 to 180 mT of remanence and PC95 at about 85: the Br row at 25 °C reads 180, 170 and 85 mT for the three of them in the material characteristics list. The same TDK document gives the B_sat to hold them against: Bs at 100 °C is 420, 450 and 410 mT for the same three. Against a B_sat of order 400 mT, a PC95 core starts a burst with about a fifth of its headroom already spent, and a PC47 or PC90 one with nearly half of it gone [derived, 85/400 and 175/400]. Those three are not the cores recommended here. Of the ones that are, only PC40 is in the same table, at 125 mT of B_r at 25 °C, the lowest of the four. N30's material sheet prints no B_r row at all, and we have not checked 77. The step from remanence to burst-mode behaviour is our reasoning, not anybody's measurement. It is also a good argument for keeping the factor-of-two volt-second margin above rather than spending it.
The last point about the core is mechanical. Do not clamp the ring hard. Ferrite is brittle and a bolt through a clamp will crack it. Even short of cracking, mechanical stress changes the magnetic properties you just measured. Hold it with a cable tie, a bed of silicone, or a printed cradle that does not squeeze. This is ordinary practice with ferrite, not something our sources say about gate transformers specifically.
The turns
Two conditions set the turns. They scale differently with frequency, so which one is binding changes as you go up the band:
by inductance
N >= sqrt(10·t_on·R_loop / A_L)
grows as sqrt(t_on)
by saturation
N >= V·t_on / (B_sat·A_e)
grows as t_onThe 10 is a sag tolerance with the arithmetic already done, so you can change it. TI's condition is that the droop over an on-time is some fraction d of the supply:
V_droop / V_supply = t_on·R / (2·L_mag) <= d
so L_mag >= t_on·R / (2d)
and the factor is 1/(2d)
d = 5% -> 10 d = 10% -> 5
d = 2% -> 25The formula above is therefore the five per cent condition. Turns go as the square root of the factor, so the sag you can tolerate translates directly into a winding you can fit.
There is a second sag figure in circulation. Richie Burnett says up to about 2 V of sag is acceptable, on his gate drive transformer waveform gallery. On a 24 V drive 2 V is 8.3 per cent, a factor of 6 rather than 10. The two criteria differ by nearly a factor of two in d and by sqrt(10/6), 29 per cent, in turns. They stop conflicting once you say which is which, and this is our reconciliation rather than either source's: design to the 5 per cent, since every turn count in this article is computed from it, and accept up to the 2 V on the scope, because that is a limit and not a target. If the window will not take the turns, relax d on purpose and you will know exactly what it costs.
The saturation term is pessimistic by a factor of two on purpose, so do not add a second safety factor on top. A push-pull transformer driven symmetrically walks the flux from -B_sat to +B_sat, so the excursion actually available is 2·B_sat and the true denominator is twice what is written. We keep the one-sided form because nothing holds the duty cycle exactly symmetric. Any imbalance leaves a DC component that walks the operating point off centre and eats the other half of the headroom. The factor of two is margin for that, not a term in the physics.
The saturation condition falls away faster. Here it is worked across the band in turns, our arithmetic in both columns. The inputs do not all come from one machine. The inductance column is 11.5 Ω of loop resistance into an A_L of
- The saturation column is a 24 V gate drive against davekni's 95.8 mm² core at the 0.24 T hot figure worked at the end of this article. His example states neither the drive voltage nor the loop, so the 24 V is the ordinary figure used elsewhere here for Burnett's sag, not his. The waveform article declines to give a turn count from that example for this reason and points here instead. The list below is that composite, so trust the trend more than the digits.
- 50 kHz: 17.0 by inductance, 10.4 by saturation.
- 250 kHz: 7.6 and 2.1.
- 460 kHz: 5.6 and 1.1.
Inductance is the binding one throughout. Saturation closes in on it as the frequency falls and is irrelevant at the top. This is why a core saturates on a big slow coil and not on a fast one, which sounds backwards until you do the sums.
On any real coil the turns are set by sag, not saturation: under about thirty per winding, in a single layer. Sag on the top or bottom of the waveform means there are not enough. Up to about 2 V of it is acceptable.
How the wire is laid
What matters here is leakage inductance, because leakage is what rings.
Wind it as tightly twisted pairs, each secondary wire paired with its own primary wire, all lying in one layer. Separate windings on opposite sides of the ring leak badly and give overshoot.
A tight twist does no harm. Twisting shrinks the loop between the two conductors, and that loop is where leakage comes from, so tighter keeps helping until the extra wire costs more than the smaller loop saves. The cost is length. At two diameters of pitch the wire runs eighty-six per cent longer than straight, which adds resistance and is also more wire to fit in one layer.
1 · Too few turns
Sag on the top and the bottom
Magnetising current too high. The core saturates before the half cycle is over, and it buzzes.
2 · Windings apart
Low frequency ringing and overshoot
Leakage. A damper does not fix it; rewinding as pairs does.
3 · Too many turns
Slow, rounded edges
Long wire: leakage and capacitance between turns both up. Top still flat.
4 · What good looks like
Flat top, steep edges, one small overshoot
Edges under 200 ns and nothing after the overshoot. The turns that get you here depend on the core.
How many
The number of transformers depends on how the bridge is modulated, not on how big it is. The common rule that "one per leg is normal" is wrong; it generalises from one board's arrangement.
- Ordinary drive, the legs held hard in antiphase: one transformer for the whole bridge. That is the norm, not a compromise.
- Legs that have to be driven independently: two. That means freewheeling, where the devices turn off in turn rather than together, and phase shift, where the modulation depth is the shift between the legs.
- More than one bridge: one per bridge is the usual answer, not a rule. Gao ran his eight-device dual bridge off two cores in 2014 and off a single large one a year later, with nothing about the bridge changing in between.
Gao's own machines show the split. He publishes as loneoceans, and both names are quoted in the corpus for the same person. QCW 1, in 2013, is a full bridge of four IGBTs on one transformer, wound by wrapping the core in Ethernet cable. Then the count changes twice on the same coil, and never because of size. The 2014 rebuild doubles the bridge to eight devices and goes to two cores, "two GDTs with a 6:5 primary : secondary ratio"; and QCW 1.5 keeps that same bridge and rewinds "the GDT to use a single large GDT core". One core for four devices, two cores for eight, then one core for eight, all from one builder. When he moved to phase shift on QCW 2 he needed the legs apart. Slawinski's UD+ runs two, one per leg, because it freewheels: "In order for freewheeling to work you must use two separate GDTs. Each GDT will be connected to one of the GDT outputs on the UD+. Each of the GDTs controls a half bridge".
Two details that sometimes get attached to this. The seven primary turns sometimes quoted for Gao were him testing the bare core with a signal generator to see whether it was worth using, not the winding he ended up with, and he never gives the turn count of the Ethernet one. A UD2.3 is also sometimes named beside the UD+ as a second two-core board, but no such revision appears in the board history or in any source we fetched.
Freewheeling does need two. That requirement comes from the mode, not from the size of the bridge.
There is a size limit on the single-output arrangement even so, and it comes from the driver rather than the core. WaskaLabs put it on the UD2.9X: "The GDT output should easily provide sufficient current for most moderately sized coils, but the single output design is not recommended for IGBTs larger than CM300" (README). The limit is how much the one output stage can push, so it moves with gate charge and frequency, not with how many cores you wound.
One core has a second cost that only shows up after something else has failed. A shorted gate is a shorted secondary, and a shorted secondary reflects into the primary as a short. On a shared core, one device failing gate-to-emitter takes the drive away from the other three. Instead of one dead transistor you have a bridge where nothing turns on properly, and the second failure follows from the first rather than from whatever caused it. Separate cores contain that. It is not a reason to wind four cores for an ordinary bridge, where the modulation still decides. But it is what separate cores get you, and it is the real cost of sharing one, more than anything on the waveform.
The trick that makes twisted pairs trivial
Gao winds the secondaries with a length of Ethernet cable, which as he puts it conveniently has eight wires inside already.
If you have no Ethernet cable there is another trick that does the same with plain hookup wire. The useful part of the cable is not the twisting, which you can do yourself, but the colour coding: after twisting, you still know which end of each wire is which. 山猫 gets the same thing from lead length. Cut each wire so one end runs short and one runs long, call the short one A and the long one B, and then twist: "由于前面已经用引线的长短标记出来了 同名端，做成双绞线也不会乱", since the dot ends have already been marked by the length of the leads, making them into twisted pairs will not confuse them (hvdiy 235771).
His recipe is four lines long and aims at one core for both jobs, "大小功率桥通吃", swallowing bridges large and small alike:
core ferrite toroid, OD 49 mm, ID 32 mm, height 19 mm
secondary 4 wires of 0.3 mm2, wound four in hand, 13 turns
primary 0.4 mm2
tested on a G4PC50UD full bridge and a CM300DY-24H full bridge, both at 50 kHzThose areas are the Chinese standard sizes and come to roughly AWG 22 and AWG 21 [derived]. Treat it as one builder's working part, not a specification. He publishes no A_L, no measured magnetising inductance and no volt-second calculation, so the thirteen turns are right for his core and not a number to carry to yours. The marking trick does transfer. It costs nothing and works on any wire.
Gao himself says only that he wound the core with Ethernet cable and that it has eight wires in it. He does not say how the primary is connected to those eight wires. The arrangement described here (one wire of each pair to the primary, the other to that pair's device, the four primary wires paralleled) is our reconstruction. We think it is right, because eight conductors and four devices only come out even that way, and it is the only arrangement in which the pairing does the job the arithmetic in this article assumes. If it were wound with a separate primary instead, the pairs would be twisted against each other rather than against the primary, and the loop argument below would not apply.
We did not make the arrangement up. Steve Ward publishes exactly this wiring for exactly this trick on his 2008 driver page: "The GDT was wound with cat-5e network wire, using the 'white' conductors as the primaries (4 in parallel) and the other 4 wires as secondaries." That is a different builder, so it still does not tell us what Gao did. It does mean the arrangement is somebody's published practice and not only our arithmetic about eight and four.
This is a better answer than hand winding, not a lazier one, for three reasons you can see in the photograph.
First, the eight wires come already paired. A full bridge wants four pairs, one per device: one wire of each goes to the primary and the other is that device's secondary. A single length of cable gives you exactly that, in the right count, with the pairing already made, so you cannot pick up the wrong strand.
The parallel connection does more than fix the ratio. The primary current splits four ways, so each conductor carries a quarter of it, while each secondary still sits against its own primary wire down the whole length of the pair. That is the main reason the cable works so well: every gate is coupled to a conductor of its own instead of all four sharing one. You get four small, tightly coupled transformers laid in one sheath on one core.
Second, the two wires of a pair never separate over the whole run. The loop between them stays as small as the geometry allows at every point, not only where you remembered to twist.
Third, the factory pitch holds. The twist is even along the entire length, which you cannot match by hand, and it sits at the tight end of the range above without the pair ever coming apart.
Look closely at the photograph and the green pair is visibly tighter than the brown. The four pairs are deliberately twisted at different rates, which is how the cable keeps them from coupling into each other. It also means the four are not identical: a different pitch is a different length, and so a slightly different leakage per pair. With four devices driven in parallel, that is four slightly different gate drives. It is small and almost certainly below what matters on a coil, but keep it in mind before you go hunting for why one device runs warmer than its neighbour. That last step is our reasoning, not a measurement.
Which way round each winding goes
The number of cores is one decision. Which end of each wire goes where is another, and getting it wrong costs a bridge on first power-up.
The two devices in a leg are driven in antiphase. On one core that means their secondaries are wound opposing: start of one to the gate, start of the other to the emitter of its opposite. Get one pair the wrong way round and both devices in that leg turn on together, which is a short across the bus through two transistors.
Winding it as pairs makes this easier: one wire of each pair goes to the primary, start to start and tail to tail, and the other is that device's secondary. If the feedback comes out wrong, turning the whole core over is a ten-second test.
Not every wound part on a coil needs this care. A current transformer for overcurrent has a rectified output and does not care which way it is wound. The feedback one does, and so does this one.
You do not have to find out on the bridge. Terminate every secondary into something that looks like a gate (a resistor of the gate resistor's value in series with a capacitor of roughly C_iss, which for these purposes is a ceramic of the right order and not a precision part). Drive the primary from the real driver at the real frequency and put the scope across each one in turn. A reversed winding is obvious on that bench: its trace is upside down next to its neighbours, at no volts and no risk. Four traces that agree are also the cheapest check that the four windings really are identical, which the single-core arrangement depends on. This is our suggestion rather than a procedure from a source. It costs two components per gate, and they are the same four traces you would otherwise be reading after the bang.
What the driver is actually driving
The driver sees a transformer plus every gate hanging off it, and the two loads behave nothing like each other.
driver current
= magnetising (N, mu, A_e)
+ gate charge (C_iss, ratio,
edge wanted)You chose the magnetising part when you picked the turns. It goes down as N², so the same core with a third more turns asks the driver for about half as much of it. This is one more side of the same trade-off. Fewer turns couple better and leak less; more turns sag less and load the driver less. You end up with a compromise, not an optimum.
The gate part is fixed. A gate is a capacitor of several nanofarads, and the edge you want sets the current: charge divided by time. This is where the ratio hurts, and it hurts as a square.
A non-unity ratio loads the driver as the square of the ratio. A 1:1.5 transformer is more than twice the load of a 1:1, for a signal one and a half times the size. It is rarely worth it, and it is the commonest reason a driver that measured fine on the bench cannot make its edges in the machine.
On a ramped coil neither term is a burst any more. Over a bang of tens of milliseconds the gate charge has to be counted over the full swing, both devices in a leg, twice a cycle, for the whole ramp. It comes out in amps average and millifarads of reservoir, which makes it a supply, not decoupling.
The one resistor that is part of this transformer
There are half a dozen resistors around a gate drive and they get confused with each other all the time. Only one of them belongs here, because only one appears in the arithmetic above.
The damping resistor in the primary loop needs the most thought, because it is not as free as it looks. It sits inside the inductance condition, so the damping it adds is paid for in turns: ten ohms costs 1.37 times the turns and thirty costs 1.90, and the extra wire brings back the leakage you wound so carefully to avoid. It also dissipates the DC that asymmetric duty leaves on the winding, so it cannot go to zero either. You want some, and no more than you need.
The rest of the resistors at that end of the drawing are covered elsewhere, split by what you are doing rather than by how close the part sits to the ring:
- The gate resistor, the diode across it, a PNP local turn-off and its
R_B, and what the negative bias costs are all one circuit, the loop between the gate and its own emitter, and they are on the gate loop's page, along with the ferrite beads, which cure an oscillation rather than a ring and are not a substitute for either. - The pull-down, the TVS and UVLO are protection: what holds a gate down when the drive is absent, wrong, or being fought by
dV/dt. Three cases, three different answers, and they are with the driver. - The current transformer burdens and the two bleeders are not part of the gate drive at all. They come up in a repair only because they sit near it on the board, so they are with the diagnosis.
One of those comes up again under "what will get you" below: the gate resistor goes at the gate, not on this transformer's primary. It follows from the turns arithmetic as well as from the gate loop. Put a resistor in the primary and you add to R_loop, which raises the turns, which brings back leakage. The full argument is on the gate loop article.
What loads it that is not a resistor at all
- Capacitance to the switching node. With a ground plane under the transformer, that capacitance plus the ground wire's inductance is a parasitic resonator. This is why the layout rule is no plane there.
- Capacitance between the windings. A push-pull gate transformer has noticeably more of it than a power transformer, and it is the path by which the switching node reaches back to the driver.
- The leads. A gate drive transformer's own leads usually carry more inductance than anything on the board, so this is a construction problem and not a routing problem.
- Solid against stranded wire, which makes very nearly no difference. Twist and lead length are what matter.
Whether to use one at all
The comparison with an opto-isolator was decided a decade ago. The real alternative now is an isolated gate driver with an isolated DC-DC supply per floating rail: the UCC21520 class of part, or the capacitive and magnetic isolators like it. If you have not costed that out, you are choosing a gate transformer out of habit.
The isolated driver does everything the ring is bad at. There is no volt-second limit, so duty cycle is yours down to DC, which is exactly the buck-modulator case below. The propagation delay is a datasheet number rather than a property of your winding. Desaturation detection, an active Miller clamp and interlock come in the same package. The Miller clamp is a real fix for the dV/dt problem, where a transformer design can only tell you to keep your loop short.
The transformer stays in the running because it carries the power as well as the signal. One passive part replaces a driver, an isolated supply, its decoupling and its own protection on every floating gate, and on a ramped coil that supply is a real supply, not a trivial part of the job. It has no silicon at the switching node to lose. It cannot be desynchronised by a common-mode edge, because it has no logic to upset. And you can wind a spare in ten minutes at two in the morning from wire you already have, which on a coil matters more than it sounds.
The number that decides it more often than cost is common-mode transient immunity. An isolated driver has a rating for it, and past that rating the part does not degrade gracefully: it drops or corrupts pulses, in a bridge, at full bus. The corpus's own threshold for anything crossing that boundary is 50 V/ns or better, and a DRSSTC edge is in that neighbourhood, not comfortably under it. A transformer has no equivalent cliff. What it has instead is interwinding capacitance, the second item in the list above, and that degrades gradually. Calling it a choice between a graceful failure and a sharp one is our framing, not a measurement.
What will get you: where the gate resistor goes, and what to probe
The resistors and the turns are one problem. Loop resistance is in the inductance condition, so anything added to it raises the turns: ten ohms costs 1.37 times the turns, thirty ohms costs 1.90. More turns is more wire, and more wire is more leakage. Add a resistor to damp the ringing and the ringing comes back through the extra leakage. That is the warning above in numbers.
Driving the loop resistance to zero is no answer either. It dissipates the DC that asymmetric duty leaves on the winding, and that keeps the core out of saturation. Leave it as it is; just do not add to it.
Do not put a ground plane under it. Capacitance to the switching node plus the inductance of the ground wire makes a parasitic resonator. This is a layout rule rather than a way to lose hardware, so it is not marked as a warning. The phasing above is.
The duty cycle has to be nearly symmetrical. The average voltage across the transformer must be zero, or direct current in the primary loop climbs until the core saturates. TI states the requirement plainly, and notes that the loop resistance is what gives you any margin at all, by dissipating the excess. It is the same resistance the turns arithmetic is built on.
On a Tesla coil this comes for free, because a resonant bridge runs at nearly fifty per cent by construction. It is also why a gate drive transformer is the wrong way to drive a buck modulator's switch, where the duty cycle is the control variable. Doing it anyway means a blocking capacitor on the primary and a DC-restoration network on the secondary. That is enough extra parts that another isolation method is usually the better choice.
Saturation and frequency also work the opposite way to what you might expect. A saturated core stops passing the signal, and it is natural to assume that running faster makes saturation more likely. It does not. Saturation is a volt-second problem: the faster the switching, the shorter each half cycle, and the fewer volt-seconds are applied per transition. The risk is at the low frequency end. Big slow coils in the tens of kilohertz are where gate transformers saturate, and a saturated one makes a loud buzz.
The one measurement that passes or fails
This measurement tells you whether the assembled bridge meets the targets above, with a number, before it carries any power.
These are the thresholds the corpus works to. The reasons for them are our reading, not anybody's stated rationale. A gate threshold is a few volts, so pickup that reaches five means the device is starting to turn on while its opposite is on. Three leaves room for the pickup being worse at full bus than at the bus you tested at.
The numbers: ratio, turns, core and inductance
- Ratio: 1:1 usually, sometimes 1:1.5 or 1:2. A non-unity ratio loads the driver as the square of it.
- Turns: under about thirty per winding.
- Core: ungapped, with enough
A_Lthat the inductance condition lands on a turn count you can fit in one layer, and with roll-off to spare at your frequency. This is deliberately not a permeability threshold. General gate-transformer advice often asks for "µrover 4000", but PC40 is 2300 and Fair-Rite 77 is 2000, so that rule excludes both cores recommended here in favour of the one sitting on its own edge. Permeability is a term in the turns, not a specification to buy against. - Edges to aim at: under 200 ns rise and fall. At 460 kHz a half cycle is 1.09 µs, so 200 ns is nearly a fifth of it at each end. While the driver is the limit, the edge is set by
t = Q_g / I_drive(halve the edge by doubling the current, and a device with twice the gate charge wants twice the driver). Once it is not, the leakage inductance sets it, becausedi/dt = V/L_leakagedoes not care how much current the driver could have supplied. To tell which regime you are in, try a bigger driver chip. If nothing changes, you need to rewind, not order parts. - Delay through the transformer itself: effectively zero. TI puts it as the signal crossing at the speed of light and says it can be treated as 0, so the total is the driver chip's delay plus whatever the secondary-side parts add. The transformer is not a term in the phase lead budget, so do not go looking for nanoseconds inside it.
- Acceptable sag: up to about 2 V on the scope, against a design target of 5 per cent, as discussed under the turns.
- Volt-seconds available: core area ×
B_sat, and it has to cover the half cycle. This is one-sided on purpose: a symmetric drive can really use2·B_sat, and the factor of two is held back against duty imbalance. Worked example, davekni's, from a real coil at about 240 kHz: 95.8 mm² at 0.22 T is 21 µV·s per turn, which at a 2.1 µs half cycle allows up to 10 V per turn [derived from his core area and that 0.22 T]. Two things pull it down from the datasheet's 0.38. The larger is heat: a high permeability core loses about 37 per cent by 100 °C, which lands on 0.24 T, the same hot figure the N30 row below carries, TDK'sBS (100 °C)of 240 mT (SIFERRIT material N30). The second is his own margin, another 8 per cent under that, which is a choice rather than a property [derived]. Rebuilding the example from 0.24 gives 23 µV·s per turn and 11 V per turn, which is what the saturation-turns list further up uses. A power ferrite loses nearer a fifth to heat.
That worked example runs at a different frequency from the core table below, which is computed at 460 kHz like the rest of the article. A half cycle at 240 kHz is 2.1 µs against 1.09 µs at 460, so the example needs 1.93 times the volt-seconds per transition that the table's operating point does. It is the harder case, and it agrees with the turns arithmetic: saturation is a low-frequency problem, and the lower-frequency example is the one that has to work hardest against it.
Cores, as turns needed where a 4300 core takes 6, with the roll-off from Snoek and the margin that leaves at 460 kHz:
- N30,
µi4300, hotB_sat240 mT: 6 turns, roll-off 349 to 465 kHz, margin 1.01. The classic for gate transformers and current transformers, and at this frequency it is sitting on its own edge. - PC40, 2300, 380 mT: 8.2 turns, roll-off 652 to 870 kHz, margin 1.89. The core out of every dismantled switching supply, so the easiest one to find, and on volt-seconds it beats N30 outright.
- Fair-Rite 77, 2000, about 340 mT: 8.8 turns, roll-off 750 to 1000 kHz, margin 2.17. Recommended in the community for gate and current transformers on small and medium DRSSTCs.
- N87, 2200, 8.4 turns, roll-off 682 to 909 kHz, margin 1.98. The standard part.
- N95, 3000: 7.2 turns. Even over temperature.
- N41, 2800: 7.4 turns. TDK marks this one as a current transformer.
- N49, 1500: 10.2 turns, roll-off 1.0 to 1.33 MHz, margin 2.90.
- PC200, 800: 13.9 turns.
- Nanocrystalline, up to 80 000,
B_sat1200 mT: 1.4, so take 2 or 3. Best on both criteria and priced accordingly. This means ribbon, wound from tape, not the powder of the same name. Nanocrystalline powder cores are a separate product with a distributed gap and a permeability two orders lower, and they belong to choosing a choke core rather than here. Do not carry 80 000 from this row into that calculation.
The turns column is 6 × sqrt(4300/µi) and the roll-off is Snoek; both are our arithmetic on published permeabilities [derived, the whole ladder]. As a check, N30's computed roll-off, 349 to 465 kHz, lands on the 400 kHz where TDK's own optimal range ends. That 400 kHz is printed, not inferred: the material sheet gives the optimum frequency range as fmin 0.01 MHz and fmax 0.40 MHz (SIFERRIT material N30). The same sheet gives N30's µi of 4300 and its 240 mT hot. PC40's µi of 2300 and its 380 mT are TDK's too, the Bs row at 100 °C in the material characteristics list, against 500 mT at 25 °C on the line above it.
The margin column is about the carrier, not the edge. Past roll-off µ falls, A_L falls with it, the magnetising inductance is lower than the catalogue promised, and the flat top of the waveform sags more than the turns arithmetic said. It does not mean a fast edge will not get through. A 200 ns edge has content out past a megahertz, and N30's margin of 1.01 does not mean that content is lost. An edge crosses this transformer through the coupling and leakage between the windings, which are geometry, and geometry has no roll-off. Permeability sets the sag and the winding sets the edge. They are different faults with different cures, and the margin column only covers the first.
What a resistor in the primary loop costs, in turns, from the inductance condition at 460 kHz:
- 11.5 Ω, the loop as it stands: 5.6 turns.
- plus 10 Ω: 7.6 turns, 1.37 times [derived, this list].
- plus 30 Ω: 10.6 turns, 1.90 times.
What goes wrong, and what each symptom means
Most faults show up on the gate waveform, and the conditions you capture it under matter as much as the trace.
Take the trace with bus voltage on. The Miller plateau is the gate charging the Miller capacitance while the switching node swings, so with no bus there is no swing and no plateau. That still does not give you a threshold. Burnett's floor for a meaningful check is 30 to 50 V, which is a floor and not a promise, and the waveform's own page covers it in full. No published figure says where the plateau starts to be representative. A trace at no volts still shows sag and leakage ringing, but it cannot show you anything the switching node does, and the expensive faults are there. It is also why the pass-or-fail measurement above is done with the bus coming up rather than at the bench.
The symptoms all appear on the same trace and their cures exclude each other, so they have a page of their own. In short: low frequency ringing is leakage and wants rewinding, high frequency ringing wants damping, rounded edges want less damping, and sag wants more turns. The usual first move is a damping resistor, and when the fault is leakage that makes things worse.
Where next
- Reading a gate waveform, the diagnosis in full.
- The gate loop is an RLC, on choosing the gate resistor, which is tangled up with this transformer's leakage.
- The gate supply on a ramped coil, where all this stops being a decoupling problem.
The gate transformer on the department diagrams is drawn as one wound core per leg, which is the arrangement a freewheeling driver needs and not the only one there is. The gates come down into it from above and the driver comes up from below; nothing is threaded through it.