SSTC gate resistor value: why the gate loop is an RLC

The gate circuit is a series RLC, and the L in it is the leakage inductance of the gate drive transformer. Pick the gate resistor before you know that leakage and you will spend a long time blaming the wrong component.

What it is and why

Z0 = sqrt(L_GDT_leakage / C_iss_total)

That is the loop's characteristic impedance, and every resistor value is judged against it. The inductance is the transformer's leakage, the capacitance is the gates you are driving, and the resistor is the only one of the three you can turn.

The resistor is one term in a circuit whose other two terms were fixed when you wound the transformer and chose the devices, so it cannot be set on its own.

What you decide

The resistor, but only after the leakage

The resistor is set against Z0, and you cannot know Z0 until the transformer is wound.

Be exact about where relative to Z0, because the two candidates are a factor of two apart and it is easy to write one and mean the other. The damping ratio of a series RLC is

zeta = R_eff / (2·Z0)

so critically damped is R_eff = 2·Z0, and Z0 on its own gives a zeta of a half: visibly underdamped, one overshoot and done. That is usually what you want. Critical damping is the fastest edge with no overshoot at all, and a little overshoot gets you a faster edge still. Z0 is therefore the bottom of the useful range, 2·Z0 is the top, and the value to use is somewhere between.

Going below Z0 is not a trade-off. Lower the resistor while the leakage stays where it is and you get ringing, not speed. Deal with the leakage first, then the resistor. In the other order you get ringing and Miller pickup, and you will blame the wrong component.

Both ends of the range are documented failures. Too low: paralleled 160N60 IGBTs with over 14 nF of C_iss and 4.7 Ω resistors gave parasitic oscillation. The symptom looked like the phase lead ceasing to work as the bus voltage rose, which points nowhere near the gate. Twelve ohms cured it. Working backwards through the criterion above, Z0 on that machine lies between the two resistors, which on 14 nF is a leakage somewhere between 0.31 and 2.0 µH [derived, L = Z0²·C_iss at 4.7 Ω and at 12]. The thread it came from is not linked here, so none of the three numbers can be checked. Too high: rounded edges, slow rise, the device spending its transition in the linear region, and heat straight into the die.

One resistor per device, always

tau = (R/2) × (2C) = R × C

Paralleling gives the same time constant as a single device. It doubles the current, not the speed, so paralleling to go faster does not work.

If the turn-off is a local one

A diode across the resistor is the small version. The fuller circuit is a diode plus a PNP transistor at the gate, which actively pulls the gate down through a device of its own instead of just bypassing the resistor on the way out. That gives you a second adjustment: R_g sets the rise and R_B sets the fall, independently, which a single resistor with a diode cannot do. How far apart the two can be set is not established. A pair of 580 ns against 200 ns has been quoted from a TI application note that is neither named nor linked, so those figures cannot be checked.

It also produces dead time by itself, because the transistor turns off as its own supply falls to zero. That makes it a fourth source to add to the three set out below, not a way around them.

R_B is not free the way a gate resistor is. It sits across the drive swing, so it draws direct current for as long as the device is held off, and the amount is simply the swing over the resistor. At 1 kΩ on ±15 V rails it is 15 mA off one rail and 30 mA across the full swing [derived, V/R]. That is a budget item and not a rounding error, and it grows as the resistor comes down. The claim that it is "of the order of a hundred milliamps" below about 1 kΩ does not follow from these rails anywhere near a kilohm and has no source under it. On a ramped coil, whatever it comes to lands on top of a gate supply that is already a real supply.

There is another cost that is easy to miss. A push-pull gate transformer naturally puts negative volts on the gate while the device is off, and that bias is what resists Miller turn-on. The PNP arrangement rectifies the swing to a single-ended positive supply and throws the negative half away. Choosing "diodes for a fast turn-off" is also a decision to give up the negative bias that both IGBT and SiC datasheets ask for. Make that decision on purpose, not by default.

Ferrite beads, which are not a third resistor

Beads on the twisted pairs are specifically for high frequency oscillation, the parasitic kind up where the gate loop's own strays resonate. The ringing the arithmetic above deals with is a different thing. Beads do not replace getting the resistor right, and they do not replace the leakage work either. Reaching for a bead because the waveform still rings is the same mistake as reaching for damping when the fault is leakage, one octave up.

The gate supply rails

Using ±12 V instead of ±15 shortens the swing by twenty per cent, and the part of the dead time that comes from the slew rate shrinks with it.

davekni: bipolar gate drive waveforms produce some dead time just due to their non-zero slew rate even without gate resistance.

Lower rails have a cost in the other direction. Here is what published builds put on the gate drive, against peak primary current. Read the warning under the table before using any of it:

20 V   100 to 126 A   Gao's QCW
±24 V  145 to 160 A   his QCW 1.5
30 V   none stated       Steve Ward

Ward states the mechanism, though not a current for his own coil: "To further exploit the pulse capabilities of the IGBT, we drive the gates to a higher voltage (30 V is typical). This lowers the volt drop, and keeps the IGBT in saturation even at extreme conduction currents." (stevehv). He says plainly that this is higher than ordinary practice. He is knowingly past the 15 V ±10 per cent the manufacturers recommend, trading short-circuit margin for a lower saturation voltage at extreme current. The thousand amps on his page is a worked example in his limiter section, not an operating point, so his row has no current. Two rows of the table are machines and the third is a practice. Ward's mechanism runs the other way just as well. Less gate voltage means more volt drop, so the twenty per cent saved on the swing is paid for in conduction loss, and ±12 V sits below every row of that table and below the ordinary 15 V as well. Which way to go is a device question rather than a gate loop one, and it depends on whether the machine is short of dead time or short of heatsink.

The table therefore does not compare gate voltages, although it was first published as if it did. Read it as what builders put on the driver, keep the two hard facts, and do not rank the rows against each other. The part sets a ceiling of ±20 V, and ordinary practice sits at 15. A published figure could be anywhere between those two, and where any of these machines actually sits is not established.

The same problem exists between amplitude and swing. One builder quoted here states a driver rail explicitly as peak to peak, and Gao's 6:5 arithmetic works whichever way it is read. If that 24 is a swing then the 20 is too, which is ±10 V, below the ordinary 15 rather than near the top of the range. None of them writes down which they mean. A gate figure from a published build therefore carries two unknowns at once, where it was measured and whether it is an amplitude, and neither can be recovered from the number.

Ward's 30 V, at least, is written down where it is applied:

Where the dead time actually comes from

There are three sources, and each is cured differently:

1. The GDT's leakage inductance, which limits di/dt. Usually the largest.
2. The gate resistors against C_iss, an RC constant.
3. The swing of the bipolar supply, which cannot be removed.

Here is the RC part worked through. The gate travels from +V to -V, a swing of 2V, against a threshold V_th:

turns off at        t = tau · ln(2V/(V + V_th))
opposite turns on   t = tau · ln(2V/(V - V_th))
dead time = the difference

At ±15 V with a 4 V threshold, turn-off is at 0.457 tau and turn-on at 1.003 tau, so the dead time is about 0.55 tau [derived, ln(30/19) against ln(30/11), difference 0.546]. Rounding both before subtracting gives 0.54, which is slightly wrong.

And a diode across the resistor changes all three of those

First, what the resistor costs you. The gate is a capacitor, so the resistor sets the current that charges and discharges it: i = ΔV/R, and the edge takes R·C_iss to get there. A resistor does not care which way the current flows, so it slows both edges equally. You only wanted it for one job, damping the ring, and you pay for it on both edges.

The cost on turn-off is the expensive one. Turn-off is when the opposite device is about to turn on, so every nanosecond this gate spends above threshold comes straight out of the dead time. It is also when the collector is slewing, and that dV/dt pushes current back into the gate through C_gc. That Miller current has to be sunk somewhere or it lifts the gate back over threshold. What sinks it is a low impedance from gate to the negative rail, and the gate resistor is exactly what keeps that impedance from being low. The resistor therefore makes the slow edge slower and also makes the device more willing to turn itself back on.

A diode in parallel fixes this, because it can tell the two directions apart. Fit it cathode towards the driver, anode at the gate. Backwards, it gives you a fast turn-on and a slow turn-off, which is wrong in the one direction that matters. It conducts only when the gate is more positive than the driver, and that happens when the driver has swung negative to turn the device off. On that edge the resistor is shorted out, and the discharge is limited by the diode's own dynamic resistance and the wire, which is close to nothing. On turn-on the driver is positive, the diode is reverse biased, and all of the current goes through the resistor as before. The resistor now only slows the edge where you did not mind the delay.

Slow on and fast off is the right way round, because shoot-through happens on turn-off.

The diode still changes the arithmetic above, in three places at once.

• The damping is now one-directional. Whatever you chose between Z0 and 2·Z0 holds on the edge that goes through the resistor. On the bypassed edge the loop is damped by the diode's own dynamic resistance, which is close to nothing, so that transition rings at whatever the leakage and C_iss decide. Work on the leakage matters more with the diode fitted, not less.
• tau is no longer one number. The 0.546 above assumes the same R·C in both directions. Bypassed, the turn-off constant collapses and the dead time comes almost entirely from the turn-on side.
• The asymmetry is what makes the dead time, and that is also the trap. Each device turns off before its opposite turns on, and cross-conduction is a shortage of dead time rather than a fault in the phase lead. Bypassing the resistor completely can remove the margin you were relying on.

There are two smaller consequences. The gate reaches the rail less one diode drop in the fast direction, so the negative bias holding the device off is that much shallower, and that bias is what resists dV/dt pickup. The diode is also one more component at the gate. Keep the emitter wire alongside it, because loop area added here adds to the inductance in the equation at the top.

Dead time also limits the snubber. Having enough charge to commutate the node is not sufficient; the transfer also has to fit in the time. At 37 ns of dead time a 470 pF snubber needs 136 ns of phase lead, and with no snubber 91 ns does it. Those come to 57.5 and 49.6 degrees, costing 46 and 35 per cent of the signal amplitude, but only with two conditions the numbers alone do not carry. The frequency is 490 kHz, and the angle is the whole lead including the delay chain, not the snubber's share. The chain is about 190 ns on the phase lead page, so the network is turning 314 and 270 ns. Taken bare, the same two figures would be 21.9 and 14.1 degrees [derived], and a reader converting them alone would get that instead.

At high frequency, then, the ceiling on snubber capacitance is set by the dead time rather than by the charge.

What will get you

For 300 to 400+ kHz operation the value is about 220 pF, roughly a fifth of the 1 nF the UD2.7 documentation gives for its 50 to 150 kHz band. The dead-time capacitor comes down as the operating frequency goes up.

On Chinese clones the designator may be different. Look for the roughly 220 pF capacitor near the comparator and identify it by function, never by silkscreen.

This is the same part the comparator's hysteresis runs through, in the pulse branch alongside R26, so "dead-time capacitor" describes what it does and not how. On a stock board that branch sets the blanking after each edge, and the dead time follows from it. Take the DC branch out, which is what converting one of these boards to self-oscillation amounts to, and the same capacitor sets the free-running frequency instead, going roughly as one over its value. 1 nF lands at the top of the 50 to 150 kHz band the documentation quotes, so the stock value belongs to a slow coil. That conversion has its own page. In both configurations the stock part is wrong for 400 kHz.

The numbers

• The loop's characteristic impedance: Z0 = sqrt(L_leakage / C_iss). Critical damping is 2·Z0; Z0 itself is a damping ratio of a half. The useful range is between the two, nearer the bottom if you want the edge and nearer the top if you want the waveform clean.
• Dead time from the RC part: about 0.55 tau at ±15 V into a 4 V threshold.
• Gate rails: ±12 V rather than ±15 takes twenty per cent off the slew component.
• A documented too-low resistor: 4.7 Ω into 14 nF oscillated; 12 Ω did not. The source thread is not linked, so the figures cannot be checked.
• UD2.x dead time capacitor: about 220 pF for 300 to 400+ kHz, against 1 to 2.2 nF for bricks at 70 to 155 kHz.
• Snubber against dead time: at 37 ns dead time, no snubber needs 91 ns of lead and 470 pF needs 136 ns.

What goes wrong

• The phase lead appears to stop working as the bus voltage rises: parasitic gate oscillation from a resistor below Z0. Nothing to do with the lead.
• Ringing that gets worse the more damping you add: it is leakage, not damping. Rewind the transformer.
• Rounded edges and a hot device with a clean-looking waveform: too much resistance, and the transition is spending time in the linear region.
• Enormous dead time on a fast coil that no lead inductor can pay back: the stock dead time capacitor is still fitted.
• Paralleled devices oscillating against each other: a shared gate resistor.

Where next

• Reading a gate waveform, because every fault above appears on the same trace and their cures conflict.
• Dead time is a fraction, on why the setting has to be normalised to the period.
• What a gate transformer is for, which covers the first term in the equation at the top.

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Figures here are from published threads and datasheets. The gate transformer on the department diagrams is drawn as one wound core per leg, the arrangement a freewheeling driver needs, though not the only one there is. Its leakage is the first term in that equation whatever the count.