Choosing a gate resistor: the gate loop is an RLC

A gate resistor is not chosen in isolation. The gate circuit is an RLC, not an RC, and the L in it belongs to the gate drive transformer. Choose the resistor first and you will spend a long time blaming the wrong component.

What it is and why

Z0 = sqrt(L_GDT_leakage / C_iss_total)

That is the loop's characteristic impedance, and it is the scale everything else is measured against. The inductance is the transformer's leakage, the capacitance is the gates you are driving, and the resistor is the only one of the three you can turn.

Which is the whole point: the resistor is not an independent setting. It is one term in a circuit whose other two terms you built when you wound the transformer and chose the devices.

What you decide

The resistor, but only after the leakage

Criterion: Z0, and you cannot know it until the transformer is wound.

Where in relation to Z0 is worth being exact about, because the two are a factor of two apart and it is easy to write one and mean the other. The damping ratio of a series RLC is

zeta = R_eff / (2·Z0)

so critically damped is R_eff = 2·Z0, and Z0 on its own is zeta of a half — visibly underdamped, one overshoot and done. Which is usually what you actually want: critical is the fastest edge with no overshoot at all, and a little overshoot buys a faster edge than that. So Z0 is the bottom of the useful range and 2·Z0 is the top of it, and the number to reach for is somewhere between.

Both ends of the range are documented failures. Too low: paralleled 160N60 IGBTs with over 14 nF of C_iss and 4.7 Ω resistors gave parasitic oscillation, and the symptom presented as the phase lead ceasing to work as the bus voltage rose, which points nowhere near the gate. Twelve ohms cured it. Too high: rounded edges, slow rise, the device spending its transition in the linear region, and heat straight into the die.

One resistor per device, always

tau = (R/2) × (2C) = R × C

Paralleling gives the same time constant as a single device. It doubles the current, not the speed, so paralleling to go faster does not work.

If the turn-off is a local one

A diode across the resistor is the small version. The fuller circuit is a diode plus a PNP transistor at the gate, which does not merely bypass the resistor on the way out but actively pulls the gate down through a device of its own. What it buys is a second knob: R_g sets the rise and R_B sets the fall, independently, which the single-resistor-plus-diode arrangement cannot do. TI's own example runs 580 ns up against 200 ns down.

It also produces dead time by itself, because the transistor turns off as its own supply falls to zero — so this is a third source to add to the three above rather than a way around them.

Ferrite beads, which are not a third resistor

Beads on the twisted pairs are for high frequency oscillation specifically — the parasitic kind, up where the gate loop's own strays resonate, not the ringing this page's arithmetic is about. They are not a substitute for getting the resistor right and they are not a substitute for the leakage work either. Reaching for a bead because the waveform still rings is the same mistake as reaching for damping when the fault is leakage, one octave up.

The gate supply rails

Using ±12 V instead of ±15 shortens the swing by twenty per cent, and the part of the dead time that comes from the slew rate goes with it.

davekni: bipolar gate drive waveforms produce some dead time just due to their non-zero slew rate even without gate resistance.

Where the dead time actually comes from

Three sources, cured differently:

1. The GDT's leakage inductance, which limits di/dt. Usually the largest.
2. The gate resistors against C_iss, an RC constant.
3. The swing of the bipolar supply, which cannot be removed.

The RC part, worked. The gate travels from +V to −V, a swing of 2V, against a threshold V_th:

turns off at        t = tau · ln(2V/(V + V_th))
opposite turns on   t = tau · ln(2V/(V - V_th))
dead time = the difference

At ±15 V with a 4 V threshold: turn-off at 0.46 tau, turn-on at 1.00 tau, so the dead time is about 0.54 tau.

And a diode across the resistor changes all three of those

Start with what the resistor is actually costing you. The gate is a capacitor, so the resistor sets the current that charges and discharges it: i = ΔV/R, and the edge takes R·C_iss to get there. A resistor does not know which way the current is going, so it charges that toll on both edges equally. But you only wanted it for one job, damping the ring, and you are paying for it twice.

The second payment is the expensive one. Turn-off is when the opposite device is about to turn on, so every nanosecond this gate spends above threshold comes straight out of the dead time. It is also when the collector is slewing, and that dV/dt pushes current back into the gate through C_gc — the Miller current, which has to be sunk somewhere or it lifts the gate back over threshold. The thing that sinks it is a low impedance from gate to the negative rail, and the gate resistor is precisely what stops that impedance being low. So the resistor makes the slow edge slower and makes the device more willing to turn itself back on.

A diode in parallel is the way out, because it is the one component that can tell the two directions apart. Cathode towards the driver, anode at the gate — that orientation is the whole of it, and getting it backwards gives you a fast turn-on and a slow turn-off, which is the wrong way round in the one direction that matters. It conducts only when the gate is the more positive of the two, which is exactly the moment the driver has swung negative to turn the device off. On that edge the resistor is shorted out and the discharge is limited by the diode's own dynamic resistance and the wire, which is close to nothing. On turn-on the driver is positive, the diode is reverse biased, and every bit of the current goes through the resistor as before. One component, and the toll is now charged on the edge you did not mind paying it on.

Slow on, fast off, which is the right way round: turn-off is the direction shoot-through lives in. But it is not free of the arithmetic above, and three numbers move at once.

• The damping is one-directional. Whatever you chose between Z0 and 2·Z0 holds on the edge that goes through the resistor. On the bypassed edge the loop is damped by the diode's own dynamic resistance, which is close to nothing, so that transition rings at whatever the leakage and C_iss decide. Work on the leakage matters more with the diode fitted, not less.
• tau is no longer one number. The 0.54 above assumes the same R·C in both directions. Bypassed, the turn-off constant collapses and the dead time comes almost entirely from the turn-on side.
• Which is the point, and also the trap. That asymmetry is the dead time: each device turns off before its opposite turns on, and cross-conduction is a shortage of dead time rather than a fault in the phase lead. So bypassing the resistor completely can remove the margin you were relying on.

Two smaller consequences. The gate reaches the rail less one diode drop in the fast direction, so the negative bias holding the device off is that much shallower, which is the bias that resists dV/dt pickup. And the diode is one more component at the gate: keep the emitter wire alongside it, because loop area added here is added to the term this whole page is about.

And that dead time is what limits your snubber. Having enough charge to commutate the node is not sufficient; the transfer also has to fit in the time. At 37 ns of dead time a 470 pF snubber needs 125 ns of phase lead, which is 55.6 degrees and 44 per cent of the signal amplitude gone. With no snubber, 80 ns does it: 47.6 degrees and 33 per cent.

What will get you

loneoceans: C33 = 220 pF works great for high frequency operation. Solder 220 pF on C33 for 300 to 400+ kHz operation.

On Chinese clones the designator may be different. Look for the roughly 220 pF capacitor near the comparator and identify it by function, never by silkscreen.

The numbers

• The loop's characteristic impedance: Z0 = sqrt(L_leakage / C_iss). Critical damping is 2·Z0; Z0 itself is a damping ratio of a half. The useful range is between the two, nearer the bottom of it if you want the edge and nearer the top if you want the waveform clean.
• Dead time from the RC part: about 0.54 tau at ±15 V into a 4 V threshold.
• Gate rails: ±12 V rather than ±15 takes twenty per cent off the slew component.
• A documented too-low resistor: 4.7 Ω into 14 nF oscillated; 12 Ω did not.
• UD2.x dead time capacitor: about 220 pF for 300 to 400+ kHz, against 1 to 2.2 nF for bricks at 70 to 155 kHz.
• Snubber against dead time: at 37 ns dead time, no snubber needs 80 ns of lead and 470 pF needs 125 ns.

What goes wrong

• The phase lead appears to stop working as the bus voltage rises. Parasitic gate oscillation from a resistor below Z0. Nothing to do with the lead.
• Ringing that gets worse the more damping you add. It is leakage, not damping. Rewind the transformer.
• Rounded edges and a hot device with a clean-looking waveform. Too much resistance; the transition is spending time in the linear region.
• Enormous dead time on a fast coil that no lead inductor can pay back. The stock dead time capacitor is still fitted.
• Paralleled devices oscillate against each other. A shared gate resistor.

Where next

• Reading a gate waveform, because every fault above appears on the same trace and their cures conflict.
• Dead time is a fraction, on why the setting has to be normalised to the period.
• What a gate transformer is for, which owns the first term in the equation at the top.

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Figures here are from published threads and datasheets. The gate transformer on the department diagrams is drawn as one wound core per leg, which is what a freewheeling driver needs. Its leakage is the first term in that equation whatever the count.