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DRSSTC switches: IGBT, MOSFET or SiC, and what each one costs

One choice that sets both the frequency you can run and how long the bridge lives. Three families, and what each of them makes you pay for elsewhere.

CommonGnd4 August 202620 min read

One choice, and it sets both the frequency you can run and how long the bridge lives. Three families, and none of them is free: what each buys is paid for somewhere else in the machine.

What decides it

Conduction first, because it is the simplest. A MOSFET's loss is I²·R, quadratic in current. An IGBT's is V_ce·I, linear. So at hundreds of amps in short pulses the IGBT wins, and at moderate current and high frequency the MOSFET does.

Switching second, and it is where SiC lives. Its losses are far below either, low enough that a builder running a phase-shift ramp puts them well under an IGBT's, and low enough that topologies which hard-switch all the way up a ramp become practical at all. The two sheets this page leans on put a size on it: the Warp2 IGBT spends 1060 µJ a transition at 33 A, 390 V and a 125 °C junction, while the SiC part spends 75 at 13.2 A, 400 V and a hotter 175 °C. Per ampere switched that is 32.1 against 5.7 µJ, a factor of 5.7 [derived, each total over its own stated current], with the conditions tilted against the SiC rather than for it.

What it charges for that is its body diode, which sits in the resonant path, and a much sharper requirement on soft switching, because its turn-on energy is the large one.

Everything below is those two paragraphs meeting a datasheet.

What you decide

Which type

Criterion: the current, and then the frequency.

An SSTC takes MOSFETs. There is no resonant primary, the current is modest, the switching frequency is as high as a DRSSTC's, and an IGBT's current tail becomes the dominant loss.
A DRSSTC takes IGBTs. Hundreds of amps in a tank, in short bangs, is exactly their ground.

Which family, within the type

Field-stop IGBTs are the de facto standard for QCW. The old trench bricks without field-stop, the CM300 and CM600 family and their relatives, are good for an ordinary DRSSTC and lose on long ramped pulses both thermally and on switching.

And a builder who fits them puts the frequency ceiling below the loading, which is not how the note above reads. 林雪猁, who moderates the Chinese Tesla board, publishes a full build guide for a module bridge on two CM300DY-24H and positions it exactly as the drop-in for a bridge of TO-247 parts (tieba 10540490049). On frequency he tells you not to bother: in his words, translated, the thing runs far more stably over-frequency than over-load, for Tesla coil work specifically. He bounds the claim himself at arcs of two metres or less, so read it as which margin gives first on a pulled module rather than as licence past the ceiling. The reason these bridges get built is in the same post and it is not performance: scrapped modules are cheap enough now that a beginner stops losing time to dead switches.

The rest of that guide is a parts list rather than an argument, and it is worth having because it is what the ordinary Chinese-market bridge is made of: a 160 × 250 × 40 mm heatsink, 5600 µF or more of bus at 400 to 450 V, a 2 µF 1200 V snubber across the module, a 1600 V 100 A rectifier block, three 330 kΩ 5 W resistors in parallel for the bleeder, and 3 × 15 mm copper bar for the busbar. One reader proposed an IXFH54N65X3 in place of the module and was told it is too small to bother with.

Superjunction MOSFETs are poor in a high frequency resonant circuit. Their non-linear Coss gives voltage overshoot and low efficiency even under soft switching.

What the family costs at the gate

Criterion: the rail, because it is not the same rail for the three, and because on an IGBT it is part of the conduction loss the first section argued from.

What published builds run is not a spread of opinions. Put the figures against peak primary current and they line up, though only two of the three rows carry a current at all:

20 V     100 to 126 A   Gao's QCW      loneoceans.com/labs/qcw/
±24 V    145 to 160 A   his QCW 1.5    loneoceans.com/labs/qcw15/
30 V     none stated    Steve Ward     stevehv.4hv.org/drsstc_design.htm

Gao states both of his rows on his own pages: a "6:5 primary : secondary ratio for 20V gate drive with 24V on the primary" against a primary that "goes up to about 126A just below my current OCD limit", and on the later machine "a +-24V IGBT gate drive from my UD2.7" against a peak that "hovers between 145 to 160A". Read that second row as the bridge and nothing else, because the same page also drives a brick "with conventional +15 -8V drive voltages": the machine runs two rails at once.

Ward gives the top of the ladder its mechanism: "To further exploit the pulse capabilities of the IGBT, we drive the gates to a higher voltage (30 V is typical). This lowers the volt drop, and keeps the IGBT in saturation even at extreme conduction currents." Higher, said as such, and knowingly above the 15 V ±10 per cent the makers recommend, as a pulse-mode technique that buys saturation voltage at extreme current and pays in short-circuit margin.

And the floor under all three is Barnkob's, whose IGBT page gives the reason along with the number: "increasing the flow of electrons by increasing the gate-emitter voltage also increases the flow of holes", "Collector-Emitter saturation voltage lowers dramatically at gate voltages above 12 Volt", and therefore "a IGBT should never be driven with less than 15 Volt". Ward at the top and Barnkob at the bottom are one argument seen from its two ends, and that page is also where the derating in section four comes from.

Two of those rows are supply rails rather than gate voltages, and the device proves it. Gao's QCW 1.5 runs "the fantastic Warp2 IGBTs from IR", whose datasheet gives an absolute maximum V_GE of ±20 V (Infineon), so "+-24V IGBT gate drive" cannot mean ±24 at the gate: it is four volts past the rating of the part he names. What survives the ladder is the pair of hard limits that bracket every device choice on this page, the part's ±20 V ceiling and Barnkob's 15 V floor. Why the rungs between them cannot be compared with each other, and the second unknown of amplitude against swing, are with the gate loop.

Read that back against the first section and the V_ce·I there stops being a property of the part. It is partly a property of how hard the gate is driven, and an IGBT on a rail chosen for some other reason pays a conduction loss that no line on its datasheet will account for.

Whichever rail you land on has to be delivered. On a ramped coil the gate supply is a real supply sized on Q_g·f, and whether it arrives through a transformer or through an isolated DC-DC per floating rail is its own decision, which the family leans on: a driver brings desaturation detection and an active Miller clamp with it, and a transformer brings no silicon sitting at the switching node to lose.

Whether to parallel

Criterion: how evenly the array shares, which is not a property of the devices in it.

Budget no more than fifty per cent extra for a pair, and only when three things are true: the devices are matched, they share a heatsink, and their gate drives are identical. Different gate delay means one of them takes all the current.

But the mechanism is thermal before it is anything else. The hotter device drops less voltage, so it takes more current, so it heats further. That is current hogging, and it is the same runaway that kills one diode of a parallel pair and leaves its twin looking untouched, which is why the symptom is nearly always one dead part rather than two. That much is ours, and it is the argument the bus page makes about diodes. Barnkob puts the figure on it: derate the current capability by 30 to 40 per cent, because across four devices there can be up to 40 per cent difference in what each one carries, with those nearest the input conducting most.

What will get you

SiC's liability is its body diode, and it is three problems rather than one. In a resonant bridge the current goes through the antiparallel diode every half cycle, and a SiC device's body diode drops far more than a silicon one: Wolfspeed's C3M0060065K gives 5.1 V at 25 °C and 4.8 at 175, stated at V_GS = -4 V and I_SD = 6.6 A. This page carried "around 3.3 V" with nothing under it. The drop moves with gate bias, so read it as a number with conditions rather than a property of the material. Anders Mikkelsen, who builds on SiC, names the other two in the same breath as the reason to keep body diode conduction short: "PN SiC diode Vf loss, minority carrier buildup, BPD growth" (HVF 3097). The last of those is bipolar degradation, and it is cumulative rather than a loss you can budget for. His answer is not to avoid SiC. It is to keep the dead time as short as practical, because the dead time is precisely the window the body diode conducts in. That makes the diode a constraint on a setting rather than a verdict on a device, and it is why this page used to say SiC was not an upgrade and no longer does.

And the resonant bridge is not the only place, so the answer is not one answer. A coil ramped by phase shift hard-switches all the way up the ramp, so what costs is switching rather than diode conduction, and there SiC wins by a lot: Anders Mikkelsen, answering a question about exactly that on HVF 3097, says the hard-switching losses during ramping follow the sine of the phase shift angle, approach zero at 180 degrees, and "compared to IGBTs, these losses are lower with SiC by a factor of between five and ten". He is not arguing from a datasheet either: the coil he says it about is his own, two SiC TO-247 devices running a line-cycle ramp, which davekni on the same thread calls possibly a record for input power from a pair of TO-247s. So the diode argument above decides the resonant case and does not decide the ramped one, and a page that gives one answer to both is answering a topology question generally.

A high collector current can latch an IGBT, after which the gate no longer turns it off. And devices without a co-packaged diode, IGW75N60T for one, need external antiparallel diodes, which go on the heatsink, because the resonant current flows through them.

The numbers

The crossover: I²R against V_ce·I. Hundreds of amps in pulses favours the IGBT; moderate current at high frequency favours the MOSFET. No figure is quoted here for either term, because both of them are yours: R_DS(on) at the junction temperature you will actually run, and V_CE(sat) at your peak current and at the gate rail above, neither of them at the sheet's headline conditions. Two numbers off two datasheets settle it. A rule of thumb will not.
IGBT frequency ceiling: a few hundred kilohertz.
TO-247 dependable peak: 250 to 300 A, and 250 for a long ontime. A named machine sits on the top of that: Daniel Kramnik's 3.5 inch DRSSTC runs an H-bridge of FGA60N65SMD in TO-247 with the over-current setpoint at 300 A, and he says where the part runs out rather than leaving it to be inferred, that he would need to move up in size to go much past it. A rule of thumb and a builder's own ceiling landing on the same figure is worth more than either alone.
Paralleling: budget 1.5 times one device, not 2.
SiC body diode forward drop: 5.1 V at 25 °C on the C3M0060065K, at V_GS = -4 V and I_SD = 6.6 A, and the drop is the smallest of its three problems: minority carrier buildup and bipolar degradation come with it, which is why the cure is a short dead time rather than a bigger heatsink.
SiC hard-switching loss against an IGBT's: a fifth to a tenth, on a builder's own phase-shift coil.
Voltage margin: a part rated at least 1.5 times the highest voltage that can reach the bridge. It is a floor, not a range. On an ordinary DRSSTC that voltage is the bus, which is why the rule gets written against the bus: from 320 V, 600 V parts. Where something between the bank and the bridge limits what arrives, the multiplier goes against that limit and not against the bank, and the second note below is that case. Lead inductance then adds overshoot on top of whichever of the two it is, at the die: one bench switching 140 A peak from a 320 V bus measured a 55 V emitter spike and a 50 V collector spike, 105 V added to the internal Vce, on a device rated 650 V, which is 2.0 times that bus, and reports the die peaking near 700 V (HVF 2498). Those two do not add up on their own: 320 plus 105 is 425, so the terminals were already near 595 V before the package added its share [derived from his 700 and 105]. That is more margin than this bullet asks for and the die still went past its rating.

The same rule is on file as a voltage, which is easier to use, and the published machines are on file against it. Barnkob writes it as an absolute instead of a multiplier: collector-emitter voltage "should be kept at a maximum of 400V for 600V devices and 800V for 1200V devices", and he gives the reason, which is that soft switching brings the spike risk the bench above measured. That is a 66 per cent derating against the usual 80, and it is the 1.5 above said backwards, since 1 over 1.5 is 0.667 [derived]. ``

 loneoceans          340 V on 600 V    57 %    [derived, all rows] Kramnik             340 on 650        52 TMaxElectronics     350 on 650        54 Jan, SiC            800 on 1200       67      exactly at it Mikkelsen QCW II    900 on 1200       75      above                    1350 on 1700       79      above this site's QCW      440 on 650       68      just above

`` Two more clear it on the bus figure alone, davekni at 240 V and flyglas at 340, but the device rating each was running is not on file here, so they are not in the table. The rule is written for IGBTs and SiC has different spike and avalanche behaviour, so Mikkelsen sitting outside it is a divergence between rule and practice rather than a fault in his design. And note where it puts this site's own arrangement. Barnkob's ratio on a 650 V part is 433 V; the buck below is held at 440 [derived]. Seven volts, and that is what "spent on purpose" looks like once it is written as a number rather than as a multiplier.

What people actually fit, for a QCW at 420 kHz and up, from one builder's bench and worth checking on yours: IXXH75N60C3D1 and STGWA75H60DFB2 gave a strange waveform and were unreliable; AOK75B60D1, AOK60B65H2AL, FGA60N65SMD and IRGP50B60D1 worked.

What goes wrong

Devices die weeks in, for no visible reason, well below Tjmax. Not the peak temperature: the size of the swing. It tears bond wires and die attach over thousands of cycles, and it is covered with the bridge.
A paralleled pair where one device is much hotter. Gate drive mismatch. One of them is taking the current.
An IGBT that will not turn off. Latch-up from a high collector current.
Voltage overshoot and poor efficiency despite soft switching. Superjunction Coss non-linearity. Wrong family for a resonant circuit.
A SiC upgrade that performed worse. The body diode is in the resonant path every half cycle, and the dead time was left where the IGBTs had it. On SiC that window is the one to shorten, not the one to be generous with.
A device that survived the bench and died on the arc. The datasheet number was a hard-switched millisecond pulse, not your duty.

Where next

The bridge and what kills it, for the failure mechanism in full, and for the half or full question, which is the decision above this one.
A pulse rating is a temperature, which is the first warning on this page worked all the way out: where the datasheet pulse comes from, and how far past it a builder will actually run a part.
Reading a gate waveform, because an over-damped or ringing gate puts any of these devices through its linear region several times per transition.

Every department diagram draws the bridge out rather than boxing it, because whether it is a full bridge or a half is the first decision, and what is in each leg is the second.

IGBTMOSFETSiC