SSTC gate waveform troubleshooting: symptom, cause, cure

Too much leakage, too little damping and too much damping all give a bad gate trace, and their fixes pull in opposite directions. Guess wrong and you turn the gate resistor the wrong way and make it worse. The usual first move, a damping resistor on a slow ring, is the wrong one.

What you are aiming at

flat top and bottom · steep edges · small overshoot at the transitions
NO RINGING AFTER THE TRANSITIONS · rise and fall under 200 ns

This is Richie Burnett's target, from his gate drive transformer waveform gallery: a run of scope captures, each labelled with the fault and what to turn for it. The list in the next section is his too. The 200 ns is where he stops asking for changes.

What goes wrong

The first five symptoms below come from only three faults, and that is where the conflict between the cures comes from. Too much leakage and too little damping both show as ringing, and the leakage ring cannot be damped out at all. Too little damping and too much damping want the same resistor turned in opposite directions. The last two are separate problems that happen to show on the same trace. Sag is a turns fault and the buzz is saturation, and the resistor cures neither.

• Low frequency ringing: too much leakage inductance. Rewind the transformer. A damping resistor does not fix this, and reaching for one is the usual first move.
• High frequency ringing: not enough damping. Add a series damper and work on the leakage as well.
• Overshoot at the transitions: not enough damping. Increase the resistor in small steps.
• Rounded edges, slow rise: too much damping. Decrease it.
• A shark fin: either over-damped, or the driver is too weak for that gate capacitance. Reduce the damper or get a bigger driver.
• Sag on the top or the bottom: not enough primary inductance, meaning too few turns. Add turns, or use a core with a higher A_L. Burnett accepts up to about 2 V of sag; that is his limit, not a target. See the numbers below.
• A loud buzz from the transformer: the core is saturating, and the risk is at the low frequency end, not the high one. See the numbers below.

What will get you

The plateau does not switch on at any particular bus voltage. Burnett's gallery was captured with the drains at nothing and shows no plateaus anywhere. His simulation then raises the supply from zero to four hundred volts, and the flat regions lengthen steadily the whole way. When you cannot reach the working bus, he asks for a check at 30 or 50 volts. He says that proves nothing unexpected is oscillating and gives some confidence that the picture will not move much as the bus comes up. That makes it a floor for a sanity check, not a threshold in the physics. Probe through an isolated supply, and expect to see the plateau. It is the device crossing its linear region, not a fault in the drive.

Don't confuse the gate with the bridge output while you are looking. They are different nodes and they go wrong in different ways. How far a low-bus reading of the bridge can be trusted is covered on the margin page.

Here is the bridge node when it is bad:

What you change, and in what order

The transformer, before the resistor

• Ratio 1:1 usually, sometimes 1:1.5 or 1:2.
• Under thirty turns per winding. Fewer turns couple better.
• An ungapped ferrite ring with enough A_L to reach the turns you need in one layer, and roll-off to spare at your frequency. That is a calculation, not a permeability to shop for, and the transformer's own page does it. Powdered iron is worse than ferrite; nanocrystalline alloys are better.
• Each winding in a single layer.

Wind it as tightly twisted pairs, each secondary wire paired with its own primary. Separate windings give high leakage and overshoot, and that is the case for pairing them. How tight is a smaller and less settled question. Extra twist does nothing once the pair already lies together, and it costs wire.

What a gate transformer is for reads the cost of that extra wire differently, and you should know that before you wind. It works out the length, 86 per cent longer than straight at two diameters of pitch, and counts it as resistance and as wire that has to fit in one layer, under a heading saying that tight is not the fault. It also says twice, about turns, that more wire is more leakage. Both articles agree that past some point tighter stops paying, and neither has measured where. Here we take that article's own rule literally and count the extra length as leakage. Twist it tight enough to stay together, and no tighter.

Single layer and twisted pairs do not conflict. The pairs lie in one layer; the conflict would come from winding layers on top of each other.

The inductance of a GDT's own leads is usually far larger than anything on the board, so this is a transformer construction problem, not a routing problem.

Then the damping

Diodes across the gate resistors give asymmetric drive and a fast turn-off. Ferrite beads on the twisted pairs deal with high frequency oscillation. Why the order matters, and what value the resistor should be, are covered in the gate loop is an RLC.

And the things that quietly spoil it

• No ground plane under the GDT. Capacitance to the switching node plus the inductance of the ground wire makes a parasitic resonator.
• A non-1:1 ratio loads the driver as the square of the ratio, so 1:1.5 is more than twice the load.
• Solid versus stranded wire makes almost no difference. Twist and lead length do.

Three resistors near the gate drive that are not part of it

These three sit near the gate drive and get mixed up with its resistors, usually during a repair. None of them can change the waveform you are reading, so a clean gate trace on a coil that still misbehaves can be any of them.

• The current transformer burdens. There are two, of different values, next to each other on the board. Swapping them changes what the driver believes about the tank and does nothing to the gates. A clean gate waveform on a coil that behaves strangely points here, not at the transformer. The values and what they are for are with the driver.
• The bleeder across the bus bank. It is a safety item and mandatory, and has nothing to do with the gates. It is listed so it is not mistaken for something optional.
• The bleeder across the inverter output. It makes the bridge output start each bang centred, so the first push has something to move. A coil with clean gates that will not start, or skips bangs, can be this, and people then go looking in the gate drive, which is the wrong end of the machine. It lives with the bridge.

The numbers

• Edges to aim at: under 200 ns rise and fall, which is where Burnett's gallery stops asking for changes.
• Acceptable sag: up to about 2 V, Burnett's figure for the droop on a good trace. It is a ceiling on the scope, not the figure to design from. Every turn count on the transformer's page is computed to a 5 per cent droop instead, and that page reconciles the two.
• Bus voltage for a meaningful measurement: 30 to 50 V, as Burnett's floor for a check, for the reason given above and not because the plateau appears there.
• Saturation: the core's V·µs rating must exceed the largest applied V·t, and V·s per turn = core area × B_sat. The worked example here is davekni's, from his own coil at about 240 kHz: 95.8 mm² at 0.22 T is 21 µV·s per turn, and at a 2.1 µs half cycle that allows 10 V per turn [derived from his core area and that 0.22 T]. Take it as his machine, not as a rule. The 2.1 µs is his half cycle, and the 0.22 T is a hot figure with his own margin already taken out of it. That is why the transformer's page rebuilds the same example on the 0.24 T hot value alone and gets 23 µV·s and 11 V per turn.

Going from volts per turn to a turn count needs a gate drive voltage, and neither davekni's example nor the note we took it from states one. Any winding given here would have an invented input inside it, so there isn't one. The turns arithmetic, with both conditions and the sag tolerance they rest on, is on the transformer's page.

The volt-seconds required fall as frequency rises, so a high frequency coil can take more voltage without saturating, and the saturation risk is at the low end. Hundreds of kilohertz is the comfortable zone; big slow coils in the tens of kilohertz are where the danger is.

And on a QCW, the gate supply is a power supply

For long bangs the gate charge has to be counted over the full rail-to-rail swing, for both devices in a leg, twice per cycle, for the whole length of the bang. That comes to amps of average current and millifarads of capacitance, so it is no longer a decoupling problem. It has its own piece.

Where next

• The gate loop is an RLC, which is where the resistor value comes from.
• What a gate transformer is for, if the question is why there is a transformer at all.
• Inside the driver, for what holds a gate down when the drive is absent or wrong. Direct drive with no transformer belongs there too. A capacitively coupled output stage can leave the gate floating once its coupling capacitor has charged, and a rail that falls while the bridge is running is what UVLO exists for. Both are covered on that page, and you cannot read either off this trace.

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On the department diagrams the GDT is drawn as one wound core per leg, which is what a freewheeling driver wants, and how many a bridge actually needs depends on how it is modulated, not on the size of the bridge. In the drawing the gates come down into the core from above and the driver comes up from below, with nothing threaded through them. A line drawn through both would be a skewer, not a winding.