Diagnosing an SSTC gate waveform: symptom, cause, cure

Three different faults look similar on a scope and their cures are mutually exclusive. Without knowing which is which you turn the resistor and make it worse, and the usual first move is the wrong one.

What you are aiming at

flat top and bottom · steep edges · small overshoot at the transitions
NO RINGING AFTER THE TRANSITIONS · rise and fall under 200 ns

That is Richie Burnett's, off his gate drive transformer waveform gallery, a run of captures with the fault named under each and what to turn for it. Everything in the next section is his list, and the 200 ns is the point at which he stops asking for changes.

What goes wrong

The first five bullets are three faults wearing different clothes, and that is the whole reason their cures conflict. Too much leakage and too little damping both arrive as ringing, and one of the two cannot be damped out at all. Too little damping and too much want the same resistor turned in opposite directions. The last two are separate problems that happen to appear on the same trace: sag is a turns fault and the buzz is saturation, and neither is cured at the resistor.

• Low frequency ringing. Too much leakage inductance. Rewind the transformer. A damping resistor does not fix this, and reaching for one is the usual first move.
• High frequency ringing. Not enough damping. Add a series damper and work on the leakage.
• Overshoot at the transitions. Not enough damping. Increase the resistor in small steps.
• Rounded edges, slow rise. Too much damping. Decrease it.
• A shark fin. Either over-damped, or the driver is too weak for that gate capacitance. Reduce the damper or get a bigger driver.
• Sag on the top or the bottom. Not enough primary inductance: too few turns. More turns, or a core with a higher A_L. Up to about 2 V of sag is acceptable, which is Burnett's limit and not a target. See the numbers below.
• A loud buzz from the transformer. The core is saturating, and the risk is at the low frequency end, not the high one. See the numbers below.

What will get you

There is no bus voltage at which the plateau switches on, and this page used to say there was. Burnett's gallery was captured with the drains at nothing and shows no plateaus anywhere; his simulation then raises the supply from zero to four hundred volts and the flat regions lengthen steadily the whole way. What he asks for is a check at 30 or 50 volts when you cannot reach the working bus, and what he says that buys is proof that nothing unexpected is oscillating and some confidence that the picture will not move much as the bus comes up. That is a floor for a sanity check, not a threshold for the physics. Probe through an isolated supply, and read the plateau as normal: it is the device crossing its linear region, not a fault in the drive.

A hundred volts belongs to a different caution, and it points the other way. On the forum thread below, Mads Barnkob tells a builder not to be frightened by what he sees under roughly 100 to 200 V of bus, because an IGBT's output capacitance is high at low collector-emitter voltage and the switching transients look far worse there than they will at working voltage. That is about the bridge rather than the gate, and it is worth carrying here only so the two numbers are not run together: 30 to 50 V is the least that makes a gate capture worth taking, and the low-bus exaggeration it warns about lives on the other node.

What you change, and in what order

The transformer, before the resistor

• Ratio 1:1 usually, sometimes 1:1.5 or 1:2.
• Under thirty turns per winding: fewer turns couple better.
• An ungapped ferrite ring with enough A_L to reach the turns you need in one layer, and roll-off to spare at your frequency, which is a calculation and not a permeability to buy against, and it is the transformer's own page that does it. Powdered iron is worse than ferrite; nanocrystalline alloys are better.
• Each winding in a single layer.

Wind it as tightly twisted pairs, each secondary wire paired with its own primary. Separate windings give high leakage and overshoot, and that is the whole of the case for pairing them. How tight is a smaller question and a less settled one, because extra twist buys nothing once the pair already lies together and it costs wire.

The inductance of a GDT's own leads is usually far larger than anything on the board, so this is a transformer construction problem and not a routing problem.

Then the damping

Diodes across the gate resistors give asymmetric drive and a fast turn-off. Ferrite beads on the twisted pairs deal with high frequency oscillation. Why the order matters, and what value the resistor should be, is the gate loop is an RLC.

And the things that quietly spoil it

• No ground plane under the GDT. Capacitance to the switching node plus the inductance of the ground wire makes a parasitic resonator.
• A non-1:1 ratio loads the driver as the square of the ratio. 1:1.5 is more than twice the load.
• Solid versus stranded wire makes almost no difference. Twist and lead length do.

Three resistors near the gate drive that are not part of it

They are here because this is where a repair happens, and a repair is exactly when they get confused with the gate drive's own resistors. Two of the three cannot touch the waveform you are reading at all. The third can, and it reaches it from the far end of the machine.

• The current transformer burdens. Two of them, different values, adjacent on the board, and swapping them changes what the driver believes about the tank rather than anything about the gates. A clean gate waveform and a coil that behaves strangely is this, not the transformer. The values and what they are for are with the driver.
• The bleeder across the bus bank, a safety item and mandatory. Nothing to do with the gates at all; listed so it is not mistaken for something optional.
• The bleeder across the inverter output, which is a power part: 6 kΩ as three 2 kΩ of 75 W each. This one does reach the gate waveform, but from the far end: residual charge on the tank gets back to the driver and comes out as glitchy switching, and the gate drive is where people then go looking, which is the wrong end of the machine. It lives with the bridge.

The numbers

• Edges to aim at: under 200 ns rise and fall, which is where Burnett's gallery stops asking for changes.
• Acceptable sag: up to about 2 V, which is Burnett putting the droop on a good trace at a couple of volts. It is a ceiling on the scope and not the figure to design from: every turn count on the transformer's page is computed to a 5 per cent droop instead, and that page reconciles the two.
• Bus voltage for a meaningful measurement: 30 to 50 V as Burnett's floor for a check, for the reason given above rather than because the plateau appears there. The 100 to 200 V in that same passage is Barnkob's, about transients at the bridge, and is not a second threshold for this measurement.
• Saturation: the core's V·µs rating must exceed the largest applied V·t, and V·s per turn = core area × B_sat. The worked example this corpus carries is davekni's, off his own coil at about 240 kHz: 95.8 mm² at 0.22 T is 21 µV·s per turn, and at a 2.1 µs half cycle that allows 10 V per turn [derived from his core area and that 0.22 T]. Take it as his machine and not as a rule. The 2.1 µs is his half cycle, and the 0.22 T is a hot figure with his own margin already taken out of it, which is why the transformer's page rebuilds the same example on the 0.24 T hot value alone and gets 23 µV·s and 11 V per turn.

And on a QCW, the gate supply is a power supply

For long bangs the gate charge has to be counted over the full rail-to-rail swing, for both devices in a leg, twice per cycle, across the whole length of the bang. That comes out in amps of average current and millifarads of capacitance, which is not a decoupling problem any more, and it is its own piece.

Where next

• The gate loop is an RLC, which is where the resistor value comes from.
• What a gate transformer is for, if the question is why there is a transformer at all.
• Inside the driver, for what holds a gate down when the drive is absent or wrong. That is where direct drive with no transformer belongs: a capacitively coupled output stage can leave the gate floating once its coupling capacitor has charged, and a rail that falls while the bridge is running is what UVLO exists for. Both are argued on that page, and neither is a thing you read off this trace.

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The GDT is drawn as one wound core per leg on the department diagrams, which is what a freewheeling driver wants; how many a bridge actually needs follows from how it is modulated and not from the size of the bridge. The gates come down into it from above and the driver comes up from below, and nothing is threaded through them: a line drawn through both would be a skewer, not a winding.