The bridge is four transistors, or two, that connect the primary across the supply one way round and then the other. The rest of the coil's electronics exists to serve it, and a lot of what goes wrong with a coil goes wrong here.
What it is and why
The secondary is a resonator. It rings at its own frequency, and to build a voltage on it you have to push it in time with that ringing, the way you push a swing. Push always in one direction and nothing happens.
The bridge takes a direct voltage from the bus and turns it into an alternating one at the coil's frequency. It is an inverter, running at a few hundred kilohertz instead of fifty.
Label the four by leg: two on the left, high and low, and two on the right. To push one way, the top-left and the bottom-right turn on together, so the primary sees the bus in one polarity. To push the other way, the other diagonal turns on: bottom-left and top-right. The two diagonals take it in turn, and the primary sees the bus reversed each half cycle.
Half or full
A half bridge puts half the bus across the primary, so for the same power it needs twice the current. Current is the expensive one, because losses go as its square. For that reason serious coils are nearly always full bridges. A half bridge also needs midpoint capacitors, and the whole primary current goes through them, so they have to be rated for it.
Two devices against four, half the cost, half the voltage on the tank, a quarter of the energy and about two thirds of the arc [derived: arc length goes as roughly the cube root of energy, and the cube root of a quarter is 0.63].
- Devices: two instead of four, so roughly half the cost of the power section.
- Current: twice as much for the same power, and conduction loss goes as its square.
- Arc: about 0.63 of a full bridge's, from a quarter of the energy and the cube-root law. Derived, not measured.
We have no count of how many coils are half bridges and how many full. A half bridge makes a sensible first machine and an unsatisfying second one. A quarter of the energy gives 0.63 of the arc, so going to a full bridge is the cheapest length you can add, and not an upgrade you want to do twice. Which devices go in either is a separate decision, and it depends more on frequency than on current: IGBT or MOSFET.
Voltage headroom
On a 650 V bus, which is what a mains doubler gives you, fit 1200 V devices. Five hundred and fifty volts of margin is reasonable under soft switching. The bus itself does not use that margin up. Nothing in a bridge is stressed by the bus voltage alone, and where the margin actually goes is in the margin is in the loop.
Here is that arrangement written out. The bridge is fed from the buck's output, not from the bank, so if the buck never goes above 440 V the bridge never sees the full bus.
mains -> DOUBLER at 650 V -> large bank -> BUCK limited to 440 V -> bridge on 650 V devicesThe doubler is there for the energy in the reservoir, not for the volts on the bridge, and the bank's page works the three arrangements. The cost is duty. One 406 J bang sags that bank from 650 V to 584, so the duty a ramp top needs is that top over 584 [derived]:
- a 400 V top: 69 per cent duty, and 1.62 times margin on a 650 V device;
- 440 V: 75 per cent, and 1.48 times;
- 560 V: 96 per cent, and 1.16 times.
A 560 V top is reachable on duty. What rules it out is the margin: 1.16 times on a 650 V device is not a margin. (A bus sagged to 514 V would put that row at 109 per cent, but getting to 514 would take 784 J out of that bank, nearly twice the bang, or a bank half the size [derived], so that case does not arise.)
The ceiling can stop holding in two ways, and neither is a firmware fault. The buck's switch can fail short, or its clamping diode can conduct on the inductor's energy return during an overcurrent event. Either way the full bus reaches the bridge and the margin is gone in one cycle. So fit a hardware clamp on the buck's output capacitor, or use bridge devices with real margin at 1200 V. Also, the buck switch's own gate supply sits on the full bus, so its isolation has to be rated for the bus, not for the ceiling.
Layout, in the order that matters
- Minimum inductance between the high and low sides at the output node. Under hard switching the current commutates between one side's transistor and the other's diode at a large di/dt, and that produces the overshoots you see on Vce. This is the commutation loop. It pulls against the spacing that contains a failure (further down), which is a different gap for a different reason.
- Overlapping copper planes for the power rails.
- Local snubber capacitors at each leg, surface mount, right at the pins.
- Generous creepage. At high frequency and high voltage, surface flashover does not behave the way it does on DC.
- No copper under the bleeder resistor.
- Gate traces thin and side by side, so the loop is small.
- No ground plane under the GDT. It makes a parasitic resonator.
Steve Ward rebuilt the DRSSTC-2 bridge around the second item after an IGBT failure at 800 V.
A bleeder across the output as well
This is a second bleeder, separate from the safety one across the bus bank on the bus page. It goes across the inverter output, and it sets the state the bridge output is left in between bangs.
The reason is davekni's, and it is on the page about the handover. The bridge output has to start centred, so that either polarity of the first half cycle can start the oscillation. If charge or device leakage has left the output sitting at the rail the first pulse drives it to, the first pulse changes nothing, there is no feedback, and the coil does not start. A resistor across the output pulls it back to the middle between bangs.
It is not the only cure. A driver that puts more than one transition on the gates before feedback arrives does not need it, because the second transition goes the other way. Nor does it fix every skipped bang. AstRii fitted 22 kΩ across his bridge output and the skipping carried on, because his fault was at the comparator input, not at the bridge.
What it does to the rest of the machine is our own reasoning, not a source's. A bang that starts with the output stuck at a rail starts from a condition the design never planned for, and the timing the phase lead was set against does not hold for its first cycles. The fault shows at the gates, and people tend to look for it at the transformer, the wrong end of the machine.
More than one bridge
First, why you cannot just fit more devices. Paralleling inside a leg looks like the cheap answer, but it hits a limit that has nothing to do with money.
Every device added hangs its own C_o(tr) on the switching node, and the lead needed to commutate that node during the dead time rises with it. Run the floor calculation on this bridge's own figures, 170 A peak at 490 kHz into 440 V with 37 ns of dead time and 794 pF a device:
devices node C ZVS floor against the 79 ns the network delivers
1 0.79 nF 36.6 ns covered
2 1.59 54.7 covered
3 2.38 72.9 covered, barely
4 3.18 91.3 short by 12 ns <- what this bridge runs
6 4.76 128.9 short by 50
8 6.35 168.1 short by 89
16 12.70 374.3 short by 295[derived, every row, on the expression that page states]. Each device adds 18 to 20 ns to the floor, and the lead stays where it is.
On this machine the limit is three devices a leg, and we are already past it. This bridge runs four, which puts it 12 ns short of its own floor. That is the same disagreement flagged on the ZVS page, not a new one.
The limit is really a ratio, so different machines hit it at different device counts. The charge to be moved is N · C_o(tr) · V_bus, and the residual current moves it, so halving the bus and doubling the current have the same effect. On the figures above, either change on its own moves the limit from three devices a leg to six, and both together move it to thirteen [derived]. A coil on a lower bus can parallel more devices, and how many will fit always depends on the rest of the machine.
The device family moves it too, and that is where the limit stops being electrical. Wolfspeed's C3M0060065K is the same 650 V class at a lower 60 mΩ, and its Rev. 5 data sheet gives an effective output capacitance, time related, of 132 pF against this part's 794, on the same 0 to 400 V definition. Six times less capacitance on the node moves the limit from three devices a leg to twenty, which is eighty in a full bridge [derived, the same expression on 132 pF]. By then the floor is no longer what limits you; the loop and the gate drive are. On silicon superjunction the limit is electrical, and on silicon carbide it is layout and money. The same sheet gives Q_rr as 110 nC against this part's 1 µC, and a body diode forward drop of 5.1 V, the trade the device page works through.
Surprisingly, the MOSFET this bridge runs is the worst of the three on this count. The Warp2 IGBT the device page quotes, IRGP50B60PD1, publishes an effective output capacitance, time related, of 215 pF, so on the same expression its limit is twelve devices a leg against the superjunction part's three. Check the definitions behind the three figures. Both MOSFET sheets state theirs over 0 to 400 V and the IGBT sheet over 0 to 80 per cent of V_CES, which is 0 to 480, so the comparison is close but not exact. Also, a limit in device count is not a limit in amperes, since the three parts do not each carry the same current.
The next step up is therefore another bridge rather than another device. Eight bridges of four are thirty two devices at a floor of 91 ns each, because every bridge commutates its own node. The same thirty two in one bridge would be eight a leg, a floor of 168 ns, and nothing on this coil delivers that. Ward never says he chose the architecture for this reason. This is our arithmetic, not his account, and it says the single big bridge would not switch.
In practice builders do use several bridges. paulsimik runs a double bridge, and Steve Ward's Fat coil runs eight. Asked for its tank values on HVF 294, Ward gives the primary capacitance as 13 nF, hedged as "I think", and names the reflected impedance as the thing he actually sizes: it maximises each bridge's output current at about 75 A, or 600 A across all eight.
There are two ways to do that, and they are not equally safe.
Transformers, which is the sound one
Each bridge drives its own transformer primary, and the secondaries go in series.
Steve Ward (HVF 294): since the secondaries are in series, their currents must be equal; if the secondary currents are equal, the primary currents must therefore be equal.
This holds even when the bridges see different voltages, from unequal busbar resistance for instance. The currents stay equal, and only each bridge's share of the power differs, in proportion to its voltage.
Ward again, on what the arrangement really is: essentially you are putting the inverters in series, rather than in parallel.
Parallel secondaries do nothing. It is the first thing people try.
Why the transformer core does not saturate
People ask this a lot, and the answer applies well beyond this arrangement.
Steve Ward (HVF 294): flux is proportional to volts × time / turns. The current in the secondary is compensated by the added current in the primary, so despite operating at a high level of current, the magnetic flux in the core is the same as if there were zero secondary current. The flux is set only by the small magnetising current.
Paultesla puts the same thing more briefly, on the same thread: a core saturates from too many volts per turn of winding, or from a DC voltage applied for too long. Load current does not saturate it.
A split tank capacitor, which is easier and is not fool-proof
Divide the capacitor bank into sections, one per bridge. It works because the capacitors' impedance at the working frequency is significant, a few ohms, so they behave as ballast resistors the way they would when paralleling transistors.
You must use the equi-drive arrangement, with capacitors on both sides of the primary. Otherwise you end up joining the bridge outputs directly, which is what you are trying to avoid. The number of banks on each side can differ, but equal is better because that maximises the impedance.
Hydron, who was building exactly this and answering Ward on that thread, simulated one half bridge failing and reported that the results are not pretty. At that point he had a working single bridge held below the 225 A rating of its 75N60s. The PCBs for the full quad-bridge were not yet ordered while he looked into overshoots on hard turn-off, and he had a much larger 24.8 nF tank in place of a transformer. Each half bridge already had its own current transformer for other reasons. Using it to catch the divergence was a plan, not a tested result, and he pairs it with a bus-interrupting switch and a fuse rather than relying on it alone.
Failure spreads by plasma
The post-mortem is Steve Ward's own, on his Fat coil, in the same thread as the sharing schemes above (HVF 294). From the wreckage, he concluded that the damage spread beyond the part that failed because plasma from the failed devices reached the ones beside them. That gives three practical rules, all his except where noted:
- Space the transistors out. Hydron, who built the split-capacitor version, adds the other half of it in the same thread: an isolated heatsink each, so there is no shared path either.
- Use materials that take the hit. Ward points at how IGBT modules use a silicone goo to contain the plasma.
- Consider an IGBT as a bus breaker. Ward runs one on a motor drive of his own and puts the interruption at about a microsecond, which limits the destruction to the device that failed first. It needs snubbers, or opening under fault current gives you an overvoltage of its own, and a high gate resistance so that the turn off is slow.
What actually kills a bridge
The heatsink sits at a baseline and the die swings above it. The die's transient rise takes microseconds and the sink's takes minutes. A sink that measures cool tells you very little about the junction doing the switching.
Peak temperature is only part of it. The size of the swing, dT, tears bond wires and die attach over thousands of cycles, long before anything reaches Tjmax. That is the likely mechanism behind bridges that die for no visible reason weeks into their life. Two people describe it on the same thread. Weston puts the stress on the joint between die and heat spreader and says a few thousand cycles can be enough at a large enough swing. Hydron adds the wire bonding, and says his own rough figures put dT past what he is willing to allow well before Tjmax. That has driven a good deal of his QCW design (HVF 1229).
We have no rule for how big that swing may be. One number often gets read as a rule and is not one: davekni's 100 ºC. He supposes a pulse rise of, in his words, say 100 ºC on a heatsink at 50, and arrives at a peak junction of 150. The 100 is his assumed input and the 150 his output. He is not subtracting from a device limit or recommending a ripple. It is also measured from the heatsink, one thermal interface further out than the case. davekni's own measure of that gap is on the pulse rating page, about 10 ºC between case and die on one TO-247 at average power. So it is a worked example on one reference point, not a limit. Choose your allowed rise deliberately, and say which two points you are measuring it between.
In one case somebody computed the number, ran the coil anyway, and lost the bridge. davekni took his device's transient thermal resistance and his own measured turn-off energy and got a peak junction temperature "a bit over 200C" for his QCW in phase-shift mode. That is an absolute peak, not a rise, so it is a different kind of figure from the 100 above, and it was checked the hard way. He decided to test it, reasoning that silicon generally does not die before about 250. It "worked great at 300Vbus" and failed on the second shot at 360 (HVF 2397). A computed 200 with 50 degrees of assumed headroom was not enough margin.
The wreckage also shows the order of events, and it is not what the damage suggests. In his words the devices fail shorted first. The bank then does the visible part: energy from 40,000 µF is enough to explode them and open the short 230 µs later, which shows on his scope as the bus going low and ringing back. Four devices of one half bridge were split. So an exploded bridge does not tell you what killed it. Current limiting at the supply does not decide the damage either. The amount of charge sitting behind the short does.
Two more points, both argued with their sources on the device page. A datasheet's first-line current rating is for hard switching, and a TO-247 is rarely dependable above about 250 to 300 A peak, set by the package's thermal mass. That peak is usually specified over a millisecond, so on a ramped coil with a long ontime read it as
- And paralleling devices does not double the current: budget no more than fifty per cent.
Here are two dead parts from Steve Ward's bench. Neither is from a coil's bridge. Both are from the inverter of his capacitor charging power supply, where he photographed what a failure leaves.
What goes wrong
- Both devices in a leg destroyed instantly on first power-up. Shoot-through: the top and the bottom of one leg were on together, which is a short across the bus through two transistors and destroys them in microseconds. Check the dead time, and check that nothing has inverted one gate signal relative to the other.
- Devices die after minutes rather than instantly, with the heatsink barely warm. Die temperature swing, not average heat. Look at the bang rate before you look at the cooling.
- Devices die at one particular tuning and nowhere else. The switching instant relative to the current zero, which is what a phase lead sets.
- Everything looked right on the scope with the bus off. The Miller plateau does not appear without bus voltage, so the gate waveform you set the gate resistor on was half the story.
The bridge is drawn out rather than boxed on every department diagram, because full or half is the first decision a builder makes, and the toggle beside the drawing shows what it does to the arc. Every figure here comes from someone else's published work or a datasheet. We did not measure any of it ourselves.