[ §1 · power stage ]

The DRSSTC bridge: half or full, layout, paralleling, what kills it

Peak temperature is not the mechanism. The size of the swing tears bond wires over thousands of cycles, a long way below anything on the datasheet.

CommonGnd4 August 202622 min read

Four transistors, or two, arranged so they can connect the primary across the supply one way round and then the other. That is the whole idea, everything else in the coil exists to serve it, and most of what goes wrong with a coil goes wrong here.

What it is and why

The secondary is a resonator. It rings at its own frequency, and to build a voltage on it you have to push it in time with that ringing, the way you push a swing. Push always in one direction and nothing happens.

So the bridge takes a direct voltage from the bus and turns it into an alternating one at the coil's frequency. That is all an inverter is, and this one just runs at a few hundred kilohertz instead of fifty.

How the four are used. Label them by leg: two on the left, high and low, and two on the right. To push one way, the top-left and the bottom-right turn on together, so the primary sees the bus in one polarity. To push the other way, the other diagonal turns on: bottom-left and top-right. The two diagonals take it in turn, and the primary sees the bus reversed each half cycle.

Half or full

A half bridge puts half the bus across the primary, so for the same power it needs twice the current, and current is the expensive one: losses go as the square of it. That is why serious coils are nearly always full bridges. A half bridge also needs midpoint capacitors, and they are not decorative: the whole primary current goes through them.

Two devices against four, half the cost, half the voltage on the tank, a quarter of the energy and about two thirds of the arc [derived: arc length goes as roughly the cube root of energy, and the cube root of a quarter is 0.63].

Devices: two instead of four, so roughly half the cost of the power section.
Current: twice as much for the same power, and conduction loss goes as its square.
Arc: about 0.63 of a full bridge's, from a quarter of the energy and the cube-root law. Derived, not measured.

Nothing in this corpus counts how many coils are one or the other, so this page will not tell you what everybody runs. What it can tell you is why the half is a sensible first machine and an unsatisfying second one: a quarter of the energy buys 0.63 of the arc, so the upgrade is the cheapest length on the bench and also the one nobody wants to do twice. Which devices go in either is a decision of its own, and it turns on frequency more than on current: IGBT or MOSFET.

Voltage headroom

On a 650 V bus, which is what a mains doubler gives you, fit 1200 V devices. Five hundred and fifty volts of margin is reasonable under soft switching. That margin is not spent on the bus, though, and where it actually goes is the margin is in the loop: the bus is the one voltage in a bridge that nothing is stressed by.

That limiting switch is the whole trick, so it is worth writing out. The bridge is not fed from the bank at all, it is fed from the buck's output, so a buck that never goes above 440 V means the bridge never sees the bus:

mains -> DOUBLER at 650 V -> large bank -> BUCK limited to 440 V -> bridge on 650 V devices

The doubler is there for the energy in the reservoir rather than for the volts on the bridge, and the bank's page works the three arrangements. What the arrangement costs here is duty. One 406 J bang sags that bank from 650 V to 584, so the duty a ramp top needs is that top over 584 [derived]:

a 400 V top: 69 per cent duty, and 1.62 times margin on a 650 V device;
440 V: 75 per cent, and 1.48 times;
560 V: 96 per cent, and 1.16 times.

Two ways the ceiling stops holding, and neither is firmware failing. The buck's switch can fail short. Or its clamping diode can conduct on the inductor's energy return during an overcurrent event. Either way the full bus arrives at the bridge and the margin is gone in one cycle. So you want a hardware clamp on the buck's output capacitor, or bridge devices with real margin at 1200 V. And the buck switch's own gate supply sits on the full bus, so its isolation has to be rated for the bus and not for the ceiling.

Layout, in the order that matters

Minimum inductance between the high and low sides at the output node. Under hard switching the current commutates between one side's transistor and the other's diode at a large di/dt, and that produces the overshoots you see on Vce. Note which distance this is. It is the commutation loop, and it pulls against the spacing that contains a failure further down this page, which is a different gap for a different reason.
Overlapping copper planes for the power rails.
Local snubber capacitors at each leg, surface mount, right at the pins.
Generous creepage. At high frequency and high voltage, surface flashover does not behave the way it does on DC.
No copper under the bleeder resistor.
Gate traces thin and side by side, so the loop is small.
No ground plane under the GDT. It makes a parasitic resonator.

The bleeder across the output is a power part

Not the one across the bus bank, which is the safety item on the bus page. A second one goes across the inverter output, and what it is there for is the charge left sitting on the tank capacitor when a bang ends.

One page carries the rule and the build both, and it is one page rather than two. Mads Barnkob's Kaizer DRSSTC III credits the finding to Steve Ward, that charge left in the tank capacitor reaches the driver and gives the coil a bad start lasting several cycles; gives the rule of thumb as a resistor in the region of 10 kΩ across the inverter output; and then fits his own, three 2 kΩ resistors in series for 6 kΩ. He also says why it goes across the inverter output rather than across the capacitor, which is that a part across the capacitor would have to stand the tens of kilovolts the tank sees. Read the 10 kΩ and the 6 kΩ as one man's rule beside one man's build, not as two machines arriving at the same answer.

The number that makes it real is the wattage: those 2 kΩ parts are 75 W each, his figure on that page. This is not a decorative bleeder soldered to a tag strip. It is a power element, it wants mounting and air like one, and it is why the layout list above has "no copper under the bleeder resistor" on it.

That resistor has a second job, and it is on the page about the handover: the bridge output has to start centred, so that either polarity of the first half cycle can start the oscillation. Same component, two reasons, and the start-up one stops the machine dead where this one only makes it misfire.

What it does to the rest of the machine, and where our reasoning starts rather than the sources': the driver suffering is theirs, above, not ours. The gate drive transformer suffers nothing on its own account, but it passes what the driver sends, so a glitchy output arrives at the gates as glitchy gate drive and the fault will be looked for at the transformer, which is the wrong end of it. And the timing: a bang that begins on a charged tank does not begin at the current zero the phase lead was set against, so the first cycles are switched somewhere other than where they were aimed. That last step is ours, not a measurement.

More than one bridge

Before how to share the current there is why you cannot simply fit more devices. Paralleling inside a leg looks like the cheap answer, and it runs into a wall that has nothing to do with money.

Every device added hangs its own C_o(tr) on the switching node, and the lead needed to commutate that node during the dead time rises with it. Run the floor calculation on this bridge's own figures, 170 A peak at 490 kHz into 440 V with 37 ns of dead time and 794 pF a device:

devices    node C     ZVS floor    against the 79 ns the network delivers
  1        0.79 nF      36.6 ns    covered
  2        1.59         54.7       covered
  3        2.38         72.9       covered, barely
  4        3.18         91.3       short by 12 ns   <- what this bridge runs
  6        4.76        128.9       short by 50
  8        6.35        168.1       short by 89
 16       12.70        374.3       short by 295

[derived, every row, on the expression that page states]. That is 18 to 20 ns of extra floor per device, against a lead that does not move.

So the wall stands at three devices a leg on this machine, and it is already behind us. Four is what this bridge runs, which puts it 12 ns short of its own floor, and that is the disagreement flagged on the ZVS page rather than a new one.

The wall is a ratio and not a device count, which is why two different machines answer it differently. The charge to be moved is N · C_o(tr) · V_bus and what moves it is the residual current, so halving the bus and doubling the current buy the same thing. On the figures above the wall goes from three devices a leg to six for either change on its own, and to thirteen for both together [derived]. A coil running a lower bus can parallel harder, and the answer to how many will fit is never a number by itself.

And the third thing that moves it is the device family, which is where the wall stops being an electrical one. Wolfspeed's C3M0060065K is the same 650 V class at a lower 60 mΩ, and its Rev. 5 data sheet gives an effective output capacitance, time related, of 132 pF against this part's 794, on the same 0 to 400 V definition. Six times less capacitance on the node moves the wall from three devices a leg to twenty, which is eighty in a full bridge [derived, the same expression on 132 pF]. At that point the floor has stopped being what limits you and the loop and the gate drive have taken over, so the honest form of the answer is that on silicon superjunction the limit is electrical and on silicon carbide it is layout and money. The same sheet gives Q_rr as 110 nC against this part's 1 µC, and a body diode forward drop of 5.1 V, which is the trade the device page works through. And the part this bridge runs is the worst of the three on this axis, which is not what anyone expects of a MOSFET. The Warp2 IGBT the device page quotes, IRGP50B60PD1, publishes an effective output capacitance, time related, of 215 pF, so on the same expression its wall stands at twelve devices a leg against the superjunction part's three. Read the three figures with their definitions attached: both MOSFET sheets state theirs over 0 to 400 V and the IGBT sheet over 0 to 80 per cent of V_CES, which is 0 to 480, so the comparison is close rather than exact. And a wall in device count is not a wall in amperes, since the three parts do not carry the same current each.

Which is the reason the next step is another bridge rather than another device. Eight bridges of four are thirty two devices at a floor of 91 ns each, because every bridge commutates its own node. The same thirty two in one bridge would be eight a leg, a floor of 168 ns, and nothing on this coil delivers that. Nothing Ward writes says he picked the architecture for that reason, so read the last step as our arithmetic rather than his account: what the numbers say is that the alternative does not switch.

In practice that is what people do. paulsimik runs a double bridge; Steve Ward's Fat coil runs eight. Asked for its tank values on HVF 294, Ward gives the primary capacitance as 13 nF, hedged as "I think", and names the reflected impedance as the thing he actually sizes: it maximises each bridge's output current at about 75 A, or 600 A across all eight.

There are two mechanisms and they are not equally safe.

Transformers, which is the sound one

Each bridge drives its own transformer primary, and the secondaries go in series.

Steve Ward (HVF 294): since the secondaries are in series, their currents must be equal; if the secondary currents are equal, the primary currents must therefore be equal.

It holds even when the bridges see different voltages, from unequal busbar resistance for instance. The currents stay equal and only the contribution to the power differs, in proportion to the voltage.

Ward again, on what the arrangement really is: essentially you are putting the inverters in series, rather than in parallel.

Parallel secondaries achieve nothing, which is worth stating because it is the first thing people try.

Why the transformer core does not saturate

This is the question almost everybody asks, and the answer is worth having because it applies far beyond this arrangement.

Steve Ward (HVF 294): flux is proportional to volts × time / turns. The current in the secondary is compensated by the added current in the primary, so despite operating at a high level of current, the magnetic flux in the core is the same as if there were zero secondary current. The flux is set only by the small magnetising current.

Paultesla puts the same thing shorter, on the same thread: a core saturates from too many volts per turn of winding, or from a DC voltage applied for too long. Not from load current.

A split tank capacitor, which is easier and is not fool-proof

Divide the capacitor bank into sections, one per bridge. It works because the capacitors' impedance at the working frequency is significant, a few ohms, so they behave as ballast resistors the way they would when paralleling transistors.

The equi-drive arrangement is mandatory: capacitors on both sides of the primary. Otherwise you are forced to join the bridge outputs directly, which is the thing being avoided. The number of banks on each side can differ, but equal is better because that maximises the impedance.

Hydron, who was building exactly this and answering Ward on that thread, simulated one half bridge failing and reported that the results are not pretty. Read what he had at that point: a working single bridge held below the 225 A rating of its 75N60s, with the PCBs for the full quad-bridge unordered while he looked at the overshoots he was seeing on hard turn-off, and a much larger 24.8 nF tank in place of a transformer. The separate current transformer on each half bridge was already there for other reasons; using it to catch the divergence was the plan, not the result, and he pairs it with a bus-interrupting switch and a fuse rather than relying on it alone.

Failure spreads by plasma

The post-mortem is Steve Ward's own, on his Fat coil, in the same thread as the sharing schemes above (HVF 294). His reading of the wreckage is that the damage was wider than the part that failed because plasma from the failed devices reached the ones beside them. Which gives three practical rules, all his except where noted:

Space the transistors out. Hydron, who built the split-capacitor version, adds the other half of it in the same thread: an isolated heatsink each, so there is no shared path either.
Use materials that take the hit. Ward points at how IGBT modules use a silicone goo to contain the plasma.
Consider an IGBT as a bus breaker. Ward runs one on a motor drive of his own and puts the interruption at about a microsecond, which limits the destruction to the device that failed first. It needs snubbers, or opening under fault current gives you an overvoltage of its own, and a high gate resistance so that the turn off is slow.

What actually kills a bridge

The heatsink is a baseline and the die swings above it. The die's transient rise happens in microseconds and the sink's in minutes, so the two are not comparable and a sink that measures cool tells you very little about the junction that is doing the switching.

And it is not only the peak temperature. The size of the swing, dT, tears bond wires and die attach over thousands of cycles, long before anything reaches Tjmax. That is the likely mechanism behind bridges that die for no visible reason weeks into their life, and it is two men's on the same thread: Weston puts the stress on the joint between die and heat spreader and says a few thousand cycles can be enough at a large enough swing, and Hydron adds the wire bonding and says his own rough figures put dT past what he is willing to allow well before Tjmax, which has driven a good deal of his QCW design (HVF 1229).

There is one published rule for how big that swing may be, and one number that is often read as a second rule and is not. Mads Barnkob is the rule: keep the ripple between junction and case below 30 ºC, and the same page shows what that is the difference of, a junction wanted under 80 ºC over a case cooled to 50. His reason is life rather than survival and he names it, that these are often second hand bricks of unknown history and what is being protected is the die attach and the bond wires. The other number is davekni's 100 ºC, and it runs the other way round: he supposes a pulse rise of, in his words, say 100 ºC on a heatsink at 50, and arrives at a peak junction of 150. The 100 is his assumed input and the 150 his output. No device limit is being subtracted from, and no ripple is being recommended. Which is why the two cannot simply be divided. Barnkob's 30 is junction against case; davekni's 100 is junction against heatsink, one thermal interface further out. This corpus has davekni's own measure of that gap on the pulse rating page, about 10 ºC between case and die on one TO-247 at average power. So what you have is one recommendation, on one reference plane, and one worked illustration on another. Pick your allowed rise deliberately, and say which two points you are measuring it between.

And there is one case where somebody computed the number, ran the coil anyway, and lost the bridge. davekni took his device's transient thermal resistance and his own measured turn-off energy and got a peak junction temperature "a bit over 200C" for his QCW in phase-shift mode. That is an absolute peak rather than a rise, so it is not a third figure on the axis above; it is the check the axis never gets. He decided to test it on the reasoning that silicon generally does not die before about 250, and it "worked great at 300Vbus" and failed on the second shot at 360 (HVF 2397). A computed 200 with 50 degrees of headroom to the belief was not enough margin. The wreckage also gives the order, which is worth having because it is not the one the damage suggests. In his words the devices fail shorted first, and the bank then does the visible part: energy from 40,000 µF is enough to explode them and open the short 230 µs later, which shows on his scope as the bus going low and ringing back. Four devices of one half bridge were split. So an exploded bridge is not evidence of what killed it, and current limiting at the supply is not what decides the damage: what decides it is how much charge sits behind the short. A second builder names that as a design reason rather than as an accident. dr. kilovolt, who built a phase-shift SiC full bridge, gives two main drawbacks of the topology and the second is this one: "if the bridge fails, it goes with a loud bang, all of the stored energy dumps into it and you end up with charred parts and possibly also the PCB" (HVF 1073). His remedy is the arrangement rather than the protection: two converters effectively in series let a simple circuit save the survivor and keep the storage capacitors out of it, "resulting in a silent failure". He says he would use a classic buck for the modulation in his next QCW, which is the machine this site is built around.

What goes wrong

Both devices in a leg destroyed instantly on first power-up. Shoot-through: the top and the bottom of one leg were on together, which is a short across the bus through two transistors and destroys them in microseconds. Check the dead time, and check that nothing has inverted one gate signal relative to the other.
Devices die after minutes rather than instantly, with the heatsink barely warm. Die temperature swing, not average heat. Look at the bang rate before you look at the cooling.
Devices die at one particular tuning and nowhere else. The switching instant relative to the current zero, which is what a phase lead sets.
Everything looked right on the scope with the bus off. It would. The Miller plateau does not appear without bus voltage, so the gate waveform you set the gate resistor on was half the story.

The bridge is drawn out rather than boxed on every department diagram, because whether it is a full one or a half is the first decision anybody makes, and the toggle beside the drawing shows what the arc does about it. Every figure here is somebody else's published work or a datasheet, and none of it was measured on this bench.

bridgeIGBTlayout