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[ §1 · timing ]

ZCS against ZVS: why switching at zero fails

DRSSTC

Turning off exactly at the current zero reads like the ideal and is the opposite. The residual current is what commutates the node, and late kills while early only heats.

CommonGnd3 min read

Turning off exactly at the current zero reads like the ideal. It is the opposite, and the reason is one line long:

switch off exactly at zero current  ->  no current left
                                    ->  nothing to recharge the leg's capacitance
                                        during the dead time
                                    ->  the opposite device turns on into the
                                        full bus, hard

The residual current at turn-off is what commutates the node. Zero current switching and zero voltage switching trade against each other, and you cannot have both.

Which one people pick

V-Troxi: I prefer to have ZVS because I'm building a QCW with long on times. davekni: I'd keep clean ZCS, even though IGBT switch-off losses are higher at higher current. You can reduce turn-off current, that is reduce phase lead, if you first reduce dead time.

Both positions are defensible and they point at different machines. Long bangs push you towards ZVS; short ones let you keep ZCS if the dead time is tight.

The consequences are not symmetric

LATE   ->  the diode conducts  ->  reverse recovery
       ->  hard turn-on of the opposite device  ->  overshoot  ->  death

EARLY  ->  turn-off at non-zero current  ->  slightly more loss
device voltagegatemargin
Watch the order, not the shapes. The voltage has to reach the bottom before the gate starts up. The shaded gap between them is the margin, and it is what the lead is bought for.

Late kills, early heats. Keep the margin on the early side, always.

What late costs, in numbers: for an IPW65R080CFD with Q_rr = 1 µC, the energy is about Q_rr × V = 440 µJ per device at 440 V, so 1.76 mJ per leg per transition. At 490 kHz that is kilowatts.

How much residual current is enough

The right criterion is that the node has to recharge within the dead time, not within the whole lead interval. The charge available in the first t_dead of that interval is:

Q(t_dead) = I_pk/(2·pi·f) · [cos(2·pi·f(dt - t_dead)) - cos(2·pi·f·dt)]
            >= C_node · V_bus

Solve for the smallest dt and you have the floor.

A worked case, four IPW65R080CFD per leg at C_o(tr) = 675 pF, 440 V, 37 ns of dead time, 170 A peak, 490 kHz:

  • no external snubber, 2.70 nF per leg: 80 ns of lead needed for ZVS;
  • 100 pF added, 3.10 nF: 90 ns;
  • 235 pF, 3.64 nF: 105 ns;
  • 470 pF, 4.58 nF: 125 ns.

Every snubber capacitor you add to soften the edges is lead you have to find somewhere else.

And on a ramp, the requirement chases itself

The lead required grows towards the end of a ramp, because the frequency is lower and the same charge has to be moved within a larger fraction of a period. But the L+R network delivers more time at the lower frequency too.

At 18.1 µH:

  • 490 kHz: 80 ns needed, 80 ns given. Margin zero.
  • 420 kHz: 92 needed, 95 given. Plus 3.
  • 376 kHz: 99 needed, 105 given. Plus 6.
  • 350 kHz: 104 needed, 112 given. Plus 8.

This is the floor half of the phase lead. The other half is the delay chain, and both are in what a phase lead actually buys. Figures here are calculations on published device data rather than measurements of ours.

ZVSZCSdead time

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