[ §1 · timing ]

DRSSTC ZCS against ZVS, and whether a snubber helps or costs

Turning off exactly at the current zero reads like the ideal and is the opposite. The residual current is what commutates the node, and late kills while early only heats.

CommonGnd4 August 202624 min read

Turning off exactly at the current zero reads like the ideal. It is the opposite, and the reason is one line long:

switch off exactly at zero current  ->  no current left
                                    ->  nothing to recharge the leg's capacitance
                                        during the dead time
                                    ->  the opposite device turns on into the
                                        full bus, hard

The residual current at turn-off is what commutates the node. Zero current switching and zero voltage switching trade against each other, and you cannot have both.

Which one people pick

Both of these are from HVF 1788, where V-Troxi could not get his UD2.7-driven QCW to switch cleanly and davekni answered him.

V-Troxi: I prefer to have ZVS because I'm building a QCW with long on times. davekni: I'd keep clean ZCS (ZVS for IGBT turn-on), even though IGBT switch-off losses are higher at higher current. You can reduce turn-off current, that is reduce phase lead, if you first reduce dead time.

They are two readings of one coil, not two machines, and the parenthesis is the half that gets dropped: davekni is not arguing for hard turn-on anywhere. He wants the turn-off clean at the current zero and the turn-on still at zero volts, and his route to it is a shorter dead time rather than more lead. That is a different remedy from V-Troxi's, on the same bridge, and the choice between them is a property of how much dead time you are carrying.

The consequences are not symmetric

LATE   ->  the diode conducts  ->  reverse recovery
       ->  hard turn-on of the opposite device  ->  overshoot  ->  death

EARLY  ->  turn-off at non-zero current  ->  slightly more loss

Watch the order, not the shapes. The voltage has to reach the bottom before the gate starts up. The shaded gap between them is the margin, and it is what the lead is bought for.

Industry gets to the same asymmetry from the other end and states it as a tuning rule. A DRSSTC is a series resonant inverter, which is also what high frequency induction heating runs on, and that field has had decades to settle where to sit relative to resonance. A survey reposted on hvdiy by 混世魔王x86 opens by making the identification, "DRSSTC实际是个串联谐振逆变器", a DRSSTC is in fact a series resonant inverter, and then works both sides of resonance (hvdiy 35902).

Below resonance the load is capacitive, the current leads the voltage, and commutation hands off from the diodes to the opposite arm's switches, which is the reverse recovery case above. Above resonance the load is inductive, the current lags, and turn-off happens before the current zero: there is some turn-off loss, but the turn-off time is short and the dead time needed is short with it. Their conclusion is a sentence a coil builder could paste straight onto a driver: "适当地控制逆变器的工作频率并使之略高于负载电路的谐振频率", control the inverter's operating frequency appropriately and keep it slightly above the load circuit's resonant frequency.

Which is early rather than late, arrived at independently, by people whose machines run continuously and cannot afford the diode. It is the same rule as this page's, and it is worth knowing it is not a Tesla coil convention.

Late kills, early heats. Keep the margin on the early side, always.

What late costs, in numbers. The loss is Q_rr × V, strictly proportional to the recovered charge, so take Q_rr as a knob rather than a fact: at 1 µC, a figure of this device class rather than a measurement of ours, that is 440 µJ per device at 440 V, 1.76 mJ per leg per transition, and kilowatts at the top of the ramp. A part with half the recovered charge costs half of every one of those numbers. Read your own Q_rr off your own datasheet and scale the column directly.

How much residual current is enough

The right criterion is that the node has to recharge within the dead time, not within the whole lead interval. The charge available in the first t_dead of that interval is:

Q(t_dead) = I_pk/(2·pi·f) · [cos(2·pi·f(dt - t_dead)) - cos(2·pi·f·dt)]
            >= C_node · V_bus

Solve for the smallest dt and you have the floor.

Take the node capacitance from C_o(tr), the time-related effective output capacitance. That is the one that gives the right charging time. Not C_oss, and not C_o(er).

A worked case, four IPW65R080CFD per leg at C_o(tr) = 794 pF, 440 V, 37 ns of dead time, 170 A peak, 490 kHz. One device holds C_o · V = 349 nC, so a leg of four holds 1.397 µC, and that factor of four against a single-device figure is a bigger bridge and not a different number:

no external snubber, 3.18 nF per leg: 91 ns of lead needed for ZVS;
100 pF added, 3.58 nF: 101 ns;
235 pF, 4.12 nF: 113 ns;
470 pF, 5.06 nF: 136 ns.

Every snubber capacitor you add to soften the edges is lead you have to find somewhere else.

The outside check this model had turns out to check nothing. Four rows were solved by hand long before this page existed, reading 80, 90, 105 and 125 ns, and reproducing them was the only corroboration here. On the old input of 675 pF the equation returns 80.3, 89.5, 102.2 and 124.5 [derived], which is why it looked like agreement. But 675 pF is on neither Infineon sheet for this part: the data sheet gives 794 typical, and on that the same equation returns 91.3, 100.7, 113.4 and 136.0 [derived], nowhere near the hand sheet. So the hand sheet was solved on the same wrong capacitance, and two calculations sharing an input agree with each other whatever it is. The rows above are the manufacturer's figure and this page now has no independent check at all, which is worth more to know than the check was.

And on a ramp, the requirement chases itself

The lead required grows towards the end of a ramp, because the frequency is lower and the same charge has to be moved within a larger fraction of a period. But the L+R network delivers more time at the lower frequency too.

The frequencies below are this machine's upper pole, 519.1 kHz falling to 463.3 on a 1.5 m arc, which is the trajectory used everywhere on this site. At 18.1 µH, with the delay chain cold:

519.1 kHz: 77 ns needed, 73 given. Minus 4.
490 kHz: 80 needed, 79 given. Minus 1.
476 kHz: 82 needed, 83 given. Plus 1.
463.3 kHz: 84 needed, 85 given. Plus 2.

The given column is the network's whole lead less the delay chain: 263 ns at the top of the ramp less the 190 ns the chain eats, and 275 less 190 at the bottom. The 190 is not a free choice here. The inductor was worked out from it, as L = R·tan(2πf·(T_d + T_ZVS))/2πf at 490 kHz, so the inductor and the chain are one decision and not two.

The reference inductor was solved on a capacitance the part does not have, and on the manufacturer's figure the same equation returns a different slug. At R = 51 Ω, f = 490 kHz and T_d = 190 ns it gives 18.16 µH on a floor of 80 ns and 19.48 µH on the 91.3 ns that Infineon's 794 pF actually produces [derived, both]. The 18.1 µH this site prints everywhere else reproduces the first and not the second, so it belongs to the old capacitance: the gap is 1.4 µH, and no rounding covers that. The figure is left at 18.1 rather than moved to 19.5, because 18.1 is a slug somebody would set and this page has no standing to redesign a bridge it has never measured. What is withdrawn is the claim that the equation returns it. And the reason it went unnoticed for so long is worth carrying: not one input to the equation is a measurement. T_d has never been measured on this machine, the floor is a calculation from C_o(tr), and the 51 Ω is the burden on Ward's UD2.1 revB schematic rather than anything read off a meter. Three unmeasured inputs will agree with an answer chosen in advance, and did.

The frequency page works the same network across the same trajectory and prints 258 and 270 where this one prints 263 and 275, and the two are not in dispute. It anchors L/R at 45 degrees at the bottom of the ramp, which is 344 ns; this page takes L/R from the inductor the reference build actually wants, 355 ns, so every row of it sits about 5 ns higher. Its fall across the ramp is 11.7 ns against the 12.2 here, and neither figure is a measurement. Read the two tables as one geometry at two anchors, and take the anchor from whichever question you are asking.

What the network sets is L/R, here 355 ns, and the burden splits that between henries and ohms: 18.1 µH against the 51 Ω a stock board carries, or 1.28 µH against 3.6. Which one to build is decided at the current transformer rather than here, and the small burden wins it, because a large one feeds the lower pole more lead than the upper.

Where the 218 comes from, because the obvious route gives a different answer and the gap is bigger than the column. Warm means the switch's t_d(off) runs about 30 per cent longer, which the phase lead page works out as 34.5 ns on its 115 ns switch. Add that to the cold midpoint of the chain, 184 ns, and you get 218.5, which is the model's expected case and the column above. Add it to the 190 this page subtracts everywhere else and you get 224.5, and the four rows read -38, -35, -34, -33 [derived] instead. The two routes differ by 6.5 ns, more than the 5.2 ns the whole cold column spans, and they differ only because 184 and 190 are two summaries of one chain. Nothing here picks between them, so read the warm rows as the shallower of the two warm cases rather than as the warm case.

Cold, the shortfall is at the start of the ramp rather than spread over it. 18.1 µH was solved at 490 kHz, the middle of this trajectory and not its top, so the first stretch runs about 4 ns inside the floor: the stretch with no arc on the coil, where the secondary Q is at its highest and the bridge is least forgiving. Solve for the inductor at the top of the pole trajectory, not at a frequency taken from the middle of it.

The margin does grow across the ramp whatever its sign, and that is the useful half of all this, because a difference between rows survives everything above. The floor rises more slowly than one over frequency, 9 per cent from 519.1 down to 463.3 kHz against 12 for 1/f, while the network's delivered time is very nearly linear in frequency across this span, its slope holding to within 3 per cent [derived, 0.2173, 0.2209 and 0.2230 ns per kHz across the three intervals between the four rows, a spread of 2.6]. That is what "the arctangent is still nearly linear here" means, and it is the one place in a QCW where something does not get harder as the arc grows.

Read that column as a shape, and read it as the cold bridge. T_d has never been measured on this machine. The 190 is a datasheet sum whose links are ranges, giving 167 to 202, and the bench figure would be accepted anywhere from 140 to 260. The 80 ns floor is a calculation too. The chain enters every row as one subtraction, so it moves all four margins together: at 167 the column reads plus 19 to plus 25, at 202 it reads minus 16 to minus 10, and the warm case above sits below all of that. The column itself spans 5.2 ns. Every one of those bands is wider than it, most by a great deal, and its own model carries three cases where it prints one. What survives is the differences between the rows, which never touch the chain, and those are what the note above is about. The absolute figures are not margin anyone can spend. Where the chain comes from, link by link, is on the phase lead page.

A snubber is a bet on that floor

Two different parts are called a snubber and they are a thousand times apart. Everything in this section is the one across the switch, measured in picofarads, which adds to the node capacitance and is paid for in phase lead. The other one sits across the module's DC terminals, is measured in microfarads, and does not touch the lead at all. This corpus carries both without ever having said so: 100, 235 and 470 pF here, against a 0.22 µF part on the margin page, 2 µF across a module on the device page, and 8.8 µF counted into a bus on the buck page. None of those pages is wrong. Reading them as one component is. The bus one exists because energy is trapped in the busbar's stray inductance when a large current stops, and it has its own sizing. Barnkob gives it as C = L_s · I²_peak / (V_transient − V_bus)² and works it at 200 nH, 2000 A, a 564 V bus and a 1000 V ceiling on a 1200 V device, which comes to about 4 µF (his snubber chapter). On the same page his rule of thumb is 0.5 µF per 100 A switched on a low inductance layout and 1 µF per 100 A on a high one, which for that machine is 10 to 20 µF, two and a half to five times his own formula. He offers both and does not reconcile them, so treat the pair as a range and the layout as the thing that decides where in it you land. His first sentence on the subject is the one to keep: a snubber "should never be used to make up for a bad circuit layout", which is the margin page arriving from the other side.

A snubber capacitor across a leg is not insurance. It is a bet, and the payoff depends entirely on whether you actually achieve zero voltage switching.

ZVS achieved. The snubber's energy returns to the tank. It costs nothing.
ZVS missed. CV²/2 goes into the die, every transition.

For four 470 pF per leg at 440 V that is 182 µJ per transition, which comes to 50 W at 14 per cent duty across both legs of a full bridge at 490 kHz [derived, C·V²/2 on 1.88 nF and 440 V, then two transitions a cycle, two legs, 490 kHz and 0.14]. The snubber doubles the penalty for failing.

The transistor snubbers itself

Before adding any, look at what is already there:

C_o(tr) = 794 pF per device   (IPW65R080CFD, typical)
t_f = 6 ns
I at turn-off = 41.6 A        (this bridge's own residual, from the phase lead page)
dV during the current fall = I·t/C = 41.6 A × 6 ns / 3.176 nF = 78.6 V

The current has already fallen while the voltage is still low. External capacitance adds little to that.

The capacitance on that line is the manufacturer's and it did not use to be. This page carried C_o(tr) = 675 pF, which is on neither the sheet for this part nor the sheet for its automotive twin, and no revision carrying it could be found. Infineon's IPW65R080CFD data sheet, Rev. 2.4, Table 5, gives 794 pF typical, for a capacitance defined there as the one "that gives the same charging time as Coss while V_DS is rising from 0 to 400V"; the IPW65R080CFDA sheet, Rev. 2.1, gives 754. Four other device figures on this page do come back from that sheet word for word, and they are named at the foot of the page. That one does not, and every number here that took it as an input has moved. The pages that took it as an input have been moved with it. The floor calculation above and the phase lead page now run on 794 pF as well: with the same 170 A, 490 kHz, 37 ns and 440 V the floor is 91.3 ns with no snubber, 100.7 at 100 pF a device and 136.0 at 470 [derived]. One thing did not survive the move, and it is on the floor page: the hand sheet that was its only outside check reproduces the 675 pF answers, so it was solved on the same wrong input and corroborated nothing.

The current in that line is the machine's own and it did not use to be. This page ran both of the calculations below on 35 A, a figure with no source on it and no derivation behind it, and the only other 35 A in this corpus belongs to Uspring's LTspice model of Jan's coil, a different machine whose measured peak is 100 A. What this bridge actually leaves at turn-off is 41.6 A, which the phase lead page states for the same bridge and which comes back a second way from its published figures: 170 A peak into sin(2π·490 kHz·80.3 ns) is 41.60 A [derived]. It survives the capacitance correction above, because the lead this coil's network actually delivers is 79 ns whatever the floor turns out to be, and 170 A into sin(2π·490 kHz·79 ns) is 40.9 A [derived]. What moves with the capacitance is the floor and the residual at the floor, not the residual on the bench.

But the superjunction non-linearity is real

C_oss   = 215 pF   (V_GS = 0 V, V_DS = 100 V, f = 1 MHz)
C_o(er) = 158 pF   (energy related, across a 0 to 400 V transition)
C_o(tr) = 794 pF   (time related, across a 0 to 400 V transition)

A spread of 3.7 times between the first and the last. In the middle of the swing the capacitance is at its minimum and there is still current flowing:

dV/dt_peak = I / (N · C_oss_min)

Worked: 41.6 A / (4 × 215 pF) = 48 V/ns [derived]. Read on the time related capacitance instead the same current gives 13.1 V/ns [derived, 41.6 A / 3.176 nF], and the factor of 3.7 between those two is the whole of the point: the rate the device actually sees mid-transition is the one taken on the smaller reading.

48 V/ns against the sheet's own ruggedness line, and the sheet does not say which rate it means. Table 2 of the same data sheet gives MOSFET dv/dt ruggedness as a maximum of 50 V/ns at V_DS = 0 to 400 V. Read as a bound on the instantaneous rate, 48 is 97 per cent of it [derived] and there is nothing left to spend. Read as a bound on the average rate across the whole swing, this bridge is at 13.1 V/ns, 26 per cent [derived], and the question does not arise. The sheet does not distinguish the two readings. Size on the first. This page has carried both "a datasheet limit of 50" and "81 per cent of the rating" with nothing cited for either. The 50 was right and unsourced; the 81 per cent was this same sum on the 35 A the page used to run [derived, 35 A / 860 pF is 40.7 V/ns, which is 81 per cent of 50]. Do not confuse the figure with the other 50 V/ns on this site, the common-mode transient immunity asked of anything crossing the isolation boundary in what RF ground is. That one is a driver's rating, not a die's, and the two are unrelated.

This is the same effect Weston describes when he says superjunction FETs are poor in high frequency resonance: a non-linear lossy Coss gives voltage spikes and lower efficiency even under ZVS.

The main defence against dV/dt pickup on the gate is a negative gate rail, not a snubber. Reaching for capacitance to fix a gate problem is how the 50 W above gets paid for nothing.

So the rule has two walls

The dead time says the capacitance must be smaller, because the charge has to be moved within it. dV/dt ruggedness says it must not be too small. The optimum is where they meet.

On this bridge they meet at zero external capacitance. The page used to print 100 to 150 pF as the answer, with no inputs under it and nothing on the page arriving at it, and that figure is withdrawn rather than defended. Both walls can now be placed.

The lower one comes straight off the ruggedness line: 41.6 A / 50 V/ns is 832 pF a leg, 208 pF a device [derived], and the four devices bring 860 pF of their own, which clears it by 3 per cent [derived] before anything is added. Three per cent is not margin, but it is the right side of the wall.

The upper one is already shut. The floor calculation gives 91 ns of lead for ZVS with no external snubber at all, 101 ns at 100 pF a device and 136 ns at 470, while the network on this coil delivers 79 ns at 490 kHz. So the dead time wall stands at zero external capacitance here and every picofarad added is lead that has to be found somewhere else. Four hundred and seventy is past it by a long way. On the datasheet's 794 pF those three rows become 91.3, 100.7 and 136.0 ns and the bare bridge is already short of its own floor, which is the disagreement flagged at the top.

Closing that shortfall, since this page keeps flagging it

Every term in the gap is now a number, so it can be priced rather than noted.

Where the 79 comes from, because it is stated on this page and derived nowhere. The network's angle is arctan(wL/R), and 18.1 µH against 51 Ω at 490 kHz is 47.54°, which on a 2041 ns period is 269.5 ns of lead. The delay chain takes 190 of it. What is left in front of the current zero is 79.5 ns [derived, all three].

And that is the cold bridge. On the warm chain of 218 ns the same network leaves 51.5 ns against the same 91.3 floor, so the shortfall goes from 11.8 ns to 39.8 [derived]. The warm case is the one that binds, which is true of everything else on this machine as well.

what closes it                       floor      what it costs
three devices a leg, not four        72.9 ns    a quarter of the bridge
bus down to 366 V                    78.9       17 per cent of the voltage
L to 19.5 µH, angle 47.5 -> 49.6     91.3       covers the cold case only
L to 23.3 µH, angle 47.5 -> 54.6     91.3       covers the warm case
a part with less C_o(tr)             38.1       the Warp2's 215 pF, at four

[derived, every row]. The inductance route is the one that stays available: davekni's practical ceiling on an L+R lead is 60°, which on this burden is 28.7 µH and 340 ns of total lead, so even the warm fix at 54.6° is inside it with room left. What it is not is free, because the burden and the coil move together and the ratio is what the network actually sets.

A published sizing rule lands on the other side of that, and which of the two capacitances above you feed it moves its answer by the same 3.7 times. T3sl4co1l writes it as C >= 2.5·Coss with R = sqrt(L_stray/Coss). Fed the 215 pF reading that is a floor of 538 pF per device, fed the 794 pF one it is 1985 [derived], and the rule itself does not say which reading it wants. Either way it puts the 470 pF at the top of this page on the wrong side, and in the opposite direction to the dead time: too little rather than too much. The two criteria point away from each other with nothing in between them. And the rule was written about a different class of device. In the same post he gives his own working value for the machine in front of him, "C around 4.7 or 10nF seems good enough", because, in the sentence before it, "Coss is a few nF for most IGBTs of useful size; it will decrease at higher voltages". Fed a superjunction MOSFET's picofarads the same rule returns picofarads, an order of magnitude below the answer he actually gave in the thread. Read that as two different jobs rather than a contradiction. His rule is for damping a layout's ringing, and the machine in that thread has 116 nH of loop inductance ringing at 3.3 MHz, which he tells the builder to fix by redoing the board rather than by sizing around. This page is sizing a transition that is meant to be lossless in the first place. Nobody has published the two against one device, so the transplant onto this example is ours and the gap between them is not yet closed by anything.

And the external antiparallel diode that never conducts

body diode of the MOSFET, V_SD = 0.9 V   (typical at I_F = 26.3 A, V_GS = 0 V)
external SiC Schottky, Vf     = 1.5 to 1.8 V

The external one will never turn on. The check takes a minute: measure both with a meter's diode range.

On a CFD, a Cool Fast Diode part, Q_rr is 1 µC typical, stated at V_R = 400 V, I_F = 26.3 A and 100 A/µs, against 10 or more for an ordinary superjunction, so its body diode recovers fast enough that nothing external is wanted. Where you might want something is the opposite part, one whose body diode is slow, and a parallel diode is still not it: with a higher forward drop it cannot take the current away from the body diode, so the recovery happens anyway. The answer there is the device.

This is the floor half of the phase lead. The other half is the delay chain, and both are in what a phase lead actually buys. Figures here are calculations on published device data rather than measurements of ours.

The device figures are Infineon's and are linked where they appear. C_oss, t_f at its stated 400 V and 26.3 A, V_SD and Q_rr come back word for word from Table 5 and Table 7 of the IPW65R080CFD data sheet, and so do C_o(tr), C_o(er) and the dv/dt ruggedness line the snubber sizing leans on. The arithmetic on them is ours. The 675 pF that used to stand in place of the first of those is gone from every page that took it as an input.

ZVSZCSdead time