[ §1 · driver design ]

DRSSTC phase lead: what it is made of, which inductor to fit

A driver that fires on the current zero is already late. The lead is how you pay that back. What it is made of, which coil delivers it, and the three worries about that coil that turn out to be unfounded.

CommonGnd3 August 202623 min read

A driver that fires on the current zero is already late. By the time the comparator has decided, the logic has propagated, the gate driver has swung and the switch has actually opened, the current it was supposed to break has been through zero and out the other side for two hundred nanoseconds. The lead is how you pay that back.

The command has to leave early because the chain between it and the switch takes time. Without the lead the switch lands on the mark to the right of zero, which is where the diode is already conducting.

What the lead is made of

Two things, and only one of them is fixed.

The first is the delay chain: the comparator, the logic, the driver, the output stage, the gate transformer and the switch itself. On the bridge these notes were written around, that is:

TL3116 comparator      7 ns
74HC logic            10 to 25
UCC27324 driver       25
FDS8958A output       10 to 20
gate transformer       5            disputed, see below
MOSFET t_d(off)      110 to 120
                     ------------
                     167 to 202     midpoint 184
                     162 to 197     without the transformer

Then take the current transformer off it, because its error is a lead and not a delay: at a 51 Ω burden that is a few nanoseconds, worth up to four per cent of the whole figure, and it is worked on its own page.

It is a datasheet sum rather than a measurement, and those ranges are what the caveat means. The switch is about five eighths of the total; the other five links together are 69 ns at the midpoint and span 57 to 82.

T_d has never been measured on this machine. It is the one item the notes behind these pages leave open: they compute about 190 ns from the datasheets and would accept anything from 140 to 260 on the bench. The component ranges above narrow that to 167 to 202, which is still a band 35 ns wide, and every margin quoted anywhere on this site is a point taken inside it. So is the other half. The 91 ns ZVS floor is a calculation from C_o(tr), 794 pF at 440 V, and not a measurement either. Both terms of every lead figure on this site are unmeasured, and no margin any of these pages reports is as wide as the band under either one.

The column is narrower than its own model, and nobody erred to make it so. The working model behind these figures carries three cases, an optimistic T_d of 156 ns, an expected 218 and a pessimistic 251, with a fifteen per cent spread either side and stray capacitance on top; its expected case is already the warm chain, not the 190 the pages quote. What reaches a page is one point out of that, and then a margin column five nanoseconds wide computed at the point. So read any single figure here as the middle of something. Take its width from this section rather than from how many digits it is printed to.

And the whole band above is the cold bridge. The switch's t_d(off) runs about 30 per cent longer once the die is warm, which moves the chain up by another 34.5 ns [derived, 30 per cent of the 115 ns switch below], in one direction, applied to every lead calculation here at once. Sized on the cold midpoint, the switch then opens 45.8 ns before the current zero instead of the floor's own 80.3 ns, which is the 80 above carried unrounded, and the bridge is left with 23.9 A at turn-off where the floor wants 41.6, which is a hard turn-on. Both currents are the same sine at 490 kHz, 170 A peak into sin(2π·f·t) taken at 80.3 ns and at 80.3 less 34.5 [derived, both]. Size on the warm number. What is not established is when the die reaches that state, inside one bang or across a run, and nothing here measures it.

That 115 is the reference machine's own switch, and the table below is not a menu to substitute into it. This bridge runs four IPW65R080CFD per leg, a CoolMOS MOSFET, and a hundred-odd nanoseconds is ordinary for one. The three parts listed underneath are IGBTs, and they are there to show the spread across devices rather than to offer alternatives for this bridge. The switch enters the chain linearly, so read it as a knob with its scaling stated, the same way Q_rr is read on the ZVS page. Put an IRGP50B60PD1's 146 ns in place of the 115 and the chain goes to 215.5 ns cold, by either route: 184.5 less 115 plus 146, or the ranges 203 to 228 taken at their middle. That moves every margin computed anywhere on this site by 31 ns the wrong way [derived], which is about six times the width of the margin column those figures go on to produce. The 30 per cent warm allowance above is a MOSFET figure as well; on an IGBT it is a different number and nothing here pins it.

The switch's share is the one that varies most, which is why the device choice is really a phase-lead choice. From the datasheets: `` IRGP50B60PD1 td(on/off) 26 / 146 ns IRG4PC50UD 46 / 140 CM600DY-24A 660 / 700 `` At 400 kHz the half period is 1.25 µs, so a fast discrete spends a tenth of it in the switch while a CM600 module spends more than half. That is the numeric reason a QCW is built on discretes and not on the big modules a DRSSTC can afford: the module's own turn-on eats a large fraction of the window the lead is trying to buy back. The figures are published, so check at least one against its datasheet. Boards outside this lineage land somewhere else again, and this page used to put a figure on one of them: a whole delay chain measured by a builder on the Chinese forum kechuang, on different parts, quoted against the 184 here. That figure is withdrawn. kechuang answers a request from this machine with a captcha gate, so the thread cannot be opened, the builder cannot be named or linked, and nothing they wrote can be checked against what this page had them saying. How long another board's chain runs is not established here, and the way to settle it is step one of the algorithm below: short the inductor out and look.

The second is the ZVS floor, and it is not a number anybody chooses. It is the amount of residual current the bridge needs in order to recharge its own node during the dead time, and it comes out of a charge balance:

Q(t_dead) = I_pk/w · [cos(w(dt - t_dead)) - cos(w·dt)] >= C_node · V_bus

Solve that for the smallest dt and you have the floor. On the reference bridge at 490 kHz it is 91 ns.

Why turning off exactly at zero is the failure case

It reads like the ideal and it is the opposite. Open the switch precisely at the current zero and there is no current left, so nothing recharges the node, so the opposite switch turns on into the full bus. What that costs is the node's own charge dumped through the device that closes on it, ½·C·V² on the C_o(tr) above: 77 µJ per device at 440 V, 307 µJ for a leg of four at 3.18 nF, and about 603 W across a full bridge's four hard turn-ons per cycle at 490 kHz [derived, all three].

That is not the 440 µJ on the ZVS page, and the two are not the same loss wearing different clothes. That one is Q_rr × V at a Q_rr of 1 µC, and it belongs to the late case, where the opposite diode conducted first and the recovered charge is what the closing device then has to sweep out. Here, by the sentence above, no diode conducted, so there is no recovered charge and the loss is capacitive only. Per device it is 440 against 65, nearly seven times, so borrowing the late figure overstates the very penalty this section exists to describe.

ZCS and ZVS trade against each other. Leftover current is the price of soft switching, and the lead is how you buy it.

That is what the lead has to be. What delivers it is a coil in series with the feedback burden resistor, and which coil is a question with a surprisingly thin paper trail, three worries attached to it that turn out to be unfounded, and one failure that keeps happening.

The algorithm

1. measure T_d           (short the inductor out and look)
2. compute T_ZVS         (from C_o(tr) and your dead time)
3. L = R · tan(360° · f · (T_d + T_ZVS)) / (2·pi·f)
4. check: 45 degrees preferred, 60 maximum
5. if it will not fit, make the driver faster rather than the coil larger

Step five is the one people skip, and the 60 in step four is davekni's: with an ordinary UD2.x lead input the theoretical maximum is 90 degrees and the practical upper limit is about 60. What makes it a ceiling is the tangent, not the signal. At 490 kHz into 51 Ω, going from 45 to 60 degrees buys 85 ns and costs 12.1 µH; going from 60 to 75 buys the same 85 ns and costs 33.1, nearly three times the wire for the same nanoseconds [derived, L = R·tan(phi)/(2·pi·f) at each angle]. Past 60 you are paying steeply for time, and the answer is a shorter delay chain, not more inductance.

This page used to give a different reason, that the amplitude across the network had collapsed by then. That is backwards. The network is fed from a current transformer, so its voltage grows with the inductor, which is why loneoceans picks a large signal on purpose.

Worth knowing where a real machine lands in that band, and the floor from step 2 has to be recomputed at each frequency rather than carried across. On the reference build the cold chain is 190 ns and the ZVS floor is 91 ns at 490 kHz but 87 at the 519.1 kHz start of the ramp, so the two sums are 281 ns and 277: 49.6° and 51.8° [derived, 360·f·(T_d + T_ZVS) at each]. This page printed 50.5 for the second of those, which is the 490 kHz floor read at the ramp's own frequency; the per-frequency floor is on the ZVS page and is what the site's calculator uses.

Warm is where this corpus's two routes part company, so both are here. The model behind these pages expects a 218 ns chain, 28 ns more than the 190, which gives 52.6° and 55.1°; scaling t_d(off) by the 30 per cent derived above adds 34.5 ns instead, giving 53.7° and 56.3° [derived, both routes, on the same two floors]. Roughly a degree apart, and neither reaches 60. The figures 52.6 and 55.7 stood here as though they followed from the 30 per cent, and they follow from the 218. So the preferred 45 is passed at every corner and the 60 is approached from below at the worst one. The band is a design range, not a target you hit.

What people actually fit

The Coilcraft 7M3 slug-tuned series, by device type. The device pairings are Gao Guangyan's, on his UD2.7 page, which is the only place they are published. The inductance spans are not his and never were: they are Coilcraft's own L min and L max, from document 112, "Slot Seven" 7 mm Tunable Inductors, where all six of these rows read at 2.5 MHz:

7M3-123, 9 to 15 µH: works well with TO-247 IGBTs.
7M3-153, 11 to 19 µH.
7M3-223, 17 to 28.
7M3-333, 25 to 41.
7M3-393, 29 to 49: works well with CM200 and CM300 bricks.
7M3-563, 42 to 70.

Every value on that list assumes a 51 Ω burden. Step 3 above has R in it, so the inductance is not a property of your coil, it is a property of your coil and the resistor the lead works against. What the network sets is L/R, about 355 ns on the reference build, and 18.1 µH is only what that costs at 51 Ω. Take the burden down to the 3.6 to 3.9 Ω that the current transformer's page argues for, and the same network wants 1.28 to 1.39 µH [derived, 355 ns × R], which is nearly seven times smaller than the 9 µH bottom of the smallest part above. There is a real decision hiding in that: the small burden is better for the transformer and better against lower-pole capture, and it puts you outside this entire parts family.

The generation before it, from Ward's own bill of materials for the UD2.1 revB, was the Coilcraft SLOT TEN-5-09 and TEN-5-10. Coilcraft's document 113, "SLOT TEN" 10 mm Tunable Inductors, gives the 5-09 as 16 µH minimum, 42 maximum and 29.4 nominal and the 5-10 as 25, 60 and 42.3, both read at 2.5 MHz. Style 5 is what that document calls "Shielded with Ferrite Core and Sleeve", and its selection guide gives style 5 an electrostatic shield and a magnetic shield listed as ferrite, which is the ferrite core in a ferrite sleeve.

Ward's original specification, since it settles an argument

From the UD2.1 revB schematic, dated March 2011:

L1 = "10 to 60 µH", with a three pin header to short it out.
R1 = 51 Ω, 2 W, the feedback burden.
C32 = 150 pF across that burden.
R17 = 5.1 Ω, 0.5 W, the overcurrent burden, on a separate transformer.

Which finally disposes of the 51 against 5.1 confusion. The 51 is the feedback burden and the only resistor L1 works against; the 5.1 is the overcurrent burden on a different ring and has nothing to do with the lead.

Ward never published his reasoning. There are no schematics or BOMs from him for the UD2.5, 2.7 or 2.9; his files stop at the 2.1 revB. The arctan(XL/R) relation appears in published form only on Mads Barnkob's UD2.x phase lead calculator, which states it as "Phase lead in Radians is calculated with ARCTAN to XL/R" and credits the idea and sketch to ArcAttack.

Mount it on the board

faraday, on HVF 317: because it was dangling there it seemed to be picking up enough EMF from the tesla coil that the signal going to the comparator got corrupted.

He adds "I could be wrong on this, but that's what I remember", so take it as one builder's recollection rather than a diagnosis. Nobody in that thread contradicts it and nobody reports trying it either.

If you wind your own, use a toroid, which closes its field, rather than an air coil. Daniel Marks (profdc9) wound his on empty Slot 7 forms off eBay and got "about 70 turns to get up to 50-60 uH inductance, which is adjustable by about 20 to 30%", in the same thread. The alternative is his other one, a bank of fixed inductors in series with a jumper across each, which has the advantage that fixed parts publish an Irms and an Isat.

The one failure that repeats

It is mechanical, and it is the tuning slug.

faraday, April 2018, on HVF 317: if I try to turn the slug down very far, not even close to bottoming, into the inductor, either the slug or the ceramic tuning tool will fracture.

Coilcraft's own explanation, via their product quality supervisor and relayed in the same post: they could not get the old coil form material a few years earlier and had to switch to a glass filled one, which is not as smooth, so the ferrite sticks to it. The tool supplier changed too, and three replacement tools were sent, of which one nearly fitted.

profdc9 cracked a bit off one. Mads Barnkob has destroyed his Slot-7 and Slot-10 inductors too. Turn them gently and do not run them to the stop.

Three worries that are not real

"One amp of feedback current is an overload." It is the design target of the whole UD2.x family. loneoceans aims for about 1 A of feedback current and picks the CT ratio to suit, so a bridge expected to run at 500 A peak gets a 500:1 transformer. WaskaLabs give the same rule of thumb for the UD2.9-X, "to keep currents around 1A at the max current you plan to see through your primary". The UD3 is specified to handle 1 A peak regardless of topology. And Ward's 51 Ω at 2 W only makes sense at hundreds of milliamps RMS.

The ampere is the design current on both paths of this family, and the two burdens are what differ. This page briefly claimed the opposite, that what is held fixed is the volts across the burden and that an amp through the 51 Ω feedback part was not a thing a driver does. Both halves are wrong and the designers say so themselves. loneoceans runs exactly that and gives the reason: "the phase lead circuit uses a relatively high voltage across the LR filter (~50+V across the 51R at 1A), and then fed through a resistor into a diode clamp circuit to make it into a reliable square signal", because a sinusoid into a comparator with a wide hysteresis band gives a variable delay and a large signal does not. Ward's protection path is the same ampere at the other end: a 5 Ω burden and a 1000 A limit is 5 V across it, and after "the diodes might drop .5V, or 1V drop total, so our output is really 4V. We would then set the comparator reference voltage to about 4V." At 1:1000 that trip is one amp of secondary current [derived]. So the burden is chosen by what each path has to do, large and clamped for the comparator's timing, small and compared for the trip, and the ampere runs through both. Ward adds the caveat that matters more than the figure: the reference "must be set experimentally", because the rectifier drop is not known in advance.

"The trim inductor will saturate, overheat or drift." Twenty years of forum archives contain no report of it. The eleven posts of HVF 317, a thread devoted specifically to choosing these parts, do not mention current once: what the builders there argue about is the slug, the tuning tool and the footprint. The one time it was seriously proposed as a cause is HVF 3485, where CJ's phase lead stopped working as the bus voltage rose and the first of davekni's two guesses was "Core saturation of phase lead adjustment inductor". It was not. CJ traced it to paralleled 160N60 IGBTs with over 14 nF of C_iss against a 4.7 Ω resistor on each gate, and 12 Ω fixed it. That is a gate loop fault and it has its own page. Two caveats keep that from acquitting the parts on the list above: the coil davekni suspected was not one of them but a home-wound adjustable core, 56 turns of 0.15 mm enamelled wire covering 15 to 40 µH, and saturation was never tested and ruled out, only overtaken by a cure that worked. What the thread does establish is that a threshold in bus voltage cannot tell a saturating core from a gate loop misbehaving, so scope the gate before you suspect the coil.

"These parts are only rated 100 mA." That figure traces to the Piconics ST series, and the trace holds up. Piconics' ST series sheet gives the ST303-3F an L range of 15 to 30 µH and an Idc Max of 40 mA, and the series a power dissipation of 200 mW max. Then look at what the part is. Its mechanical drawing on that sheet is in inches and the largest dimension on it is 0.275, under 7 mm [derived, 25.4 mm per inch], turned by a #0-80 screw. That is a microwave component, and a 7 to 10 mm slug can is an order of magnitude more volume. Coilcraft's 142, 143 and 144, the same 10 mm class as the Slot Ten, do publish a current column: document 108 runs Irms from 13.4 A on the 1½ turn 142-01J08 down to 5.5 A on the 20½ turn 143-20J12, defined in its note 5 as "Average current for a 40°C rise above 25°C ambient". Take that as a bound on the mechanics rather than on your own part, because those are the 0.05 to 1.5 µH end of the catalogue and yours is a 29 µH winding, but it does dispose of the idea that a 10 mm tunable can is inherently a 100 mA part.

What this means at the bench

Before any of it, take the secondary out. Eastern Voltage Research's controller sheet makes that the first move and names what to put in its place: "The best approach to use when tuning a DRSSTC system is to remove the secondary coil, and test with a dummy load. An empty steel coffee can is a very good dummy load and readily available." It stands in the middle of the primary, where the secondary was. It absorbs the tank's energy and it cannot build a voltage on a topload, so you can turn the setting through its whole range without anything flashing over while you are still looking for the edge. The same sheet warns the can gets "excessively hot" and suggests filling it with water for the thermal mass, and notes you can do this at the real bus voltage or a reduced one off a variac.

What the sheet does not say, and what matters for the number you walk away with: a steel can inside the primary is a shorted turn. Eddy currents in it push back against the primary's field, which pulls the tank frequency up from where it sits with the real secondary in place. So the setting the can gives you is a starting point that is safe to find, not the final one. Confirm it with the secondary back in and a short pulse.

Wind the inductor the calculator gives you, less whatever the layout already contributes.
Power up and put a probe on the bridge output.
Look for a small bump at the end of the edge. That is the optimum, not a defect.
Turn from small to large. Falling short is the more dangerous side.
Repeat it warm. A hot bridge asks for more, and the setting moves.

On a ramped coil the frequency this is all computed at does not stay put, and a network holding a constant angle then delivers a changing number of nanoseconds. Worked across a real ramp on the frequency page.

The phase lead calculator does the arithmetic and prints the zone rather than a single number, because a single number would promise a precision the inputs do not have.

ZVSphase leadinductorDRSSTC