A driver that fires on the current zero is already late. By the time the comparator has decided, the logic has propagated, the gate driver has swung and the switch has actually opened, the current has been through zero and out the other side for two hundred nanoseconds. The phase lead makes up that delay.
What the lead is made of
The lead has two parts, and only one of them is fixed.
The first is the delay chain: the comparator, the logic, the driver, the output stage, the gate transformer and the switch itself. On the bridge these notes were written around, that is:
TL3116 comparator 7 ns
74HC logic 10 to 25
UCC27324 driver 25
FDS8958A output 10 to 20
gate transformer 5 disputed, see below
MOSFET t_d(off) 110 to 120
------------
167 to 202 midpoint 184
162 to 197 without the transformerThe 5 ns for the transformer is in the budget and probably should not be. Texas Instruments' position is that a signal crosses a gate drive transformer at effectively the speed of light, so its transit can be treated as zero, and the total is the driver chip plus the edges on the secondary. On that reading the transformer does not belong in the lead budget at all. What it does contribute is interwinding capacitance, a different mechanism, covered on its own page. The line stays because it is inside the sum the inductor was solved from, and dropping it quietly would put these figures out of step with the part on the bench. It is 3 per cent of the chain and well inside the range above, so nothing here depends on it.
Then take the current transformer off it, because its error is a lead rather than a delay. At a 51 Ω burden that is a few nanoseconds, up to four per cent of the whole figure, and it is worked on its own page.
The chain is a datasheet sum, not a measurement, and the ranges show how uncertain it is. The switch is about five eighths of the total. The other five links together are 69 ns at the midpoint and span 57 to 82.
The working model is also wider than the single column it produces. It carries three cases, an optimistic T_d of 156 ns, an expected 218 and a pessimistic 251, with a fifteen per cent spread either side and stray capacitance on top. Its expected case is already the warm chain, not the 190 quoted here. What gets printed is one point out of that, and then a margin column five nanoseconds wide computed at that point. So read any single figure as the middle of a range, and take the width of the range from this section rather than from how many digits the figure is printed to.
The switch's share varies most between devices, so choosing the device is really choosing the phase lead. From the datasheets:
IRGP50B60PD1 td(on/off) 26 / 146 ns
IRG4PC50UD 46 / 140
CM600DY-24A 660 / 700At 400 kHz the half period is 1.25 µs, so a fast discrete spends a tenth of it in the switch while a CM600 module spends more than half. That is the numeric reason a QCW is built on discretes rather than on the big modules a DRSSTC can afford: the module's own turn-on eats a large part of the window the lead is trying to win back. The figures are published, so check at least one against its datasheet.
Boards from other designs land somewhere else again. An earlier version quoted a whole delay chain measured by a builder on the Chinese forum kechuang, on different parts, against the 184 here. That figure is withdrawn. kechuang answers a request from this machine with a captcha gate, so the thread cannot be opened, the builder cannot be named or linked, and nothing they wrote can be checked against what we had them saying. We do not know how long another board's chain runs. The way to find out is step one of the algorithm below: short the inductor out and look.
The second part is the ZVS floor, and nobody gets to choose it. It is the residual current the bridge needs to recharge its own node during the dead time, and it comes out of a charge balance:
Q(t_dead) = I_pk/w · [cos(w(dt - t_dead)) - cos(w·dt)] >= C_node · V_busSolve that for the smallest dt and you have the floor. On the reference bridge at 490 kHz it is 91 ns.
The two parts cannot stand in for each other. The delay chain depends on your electronics and the floor on your bridge, and fixing one does nothing for the other.
Why turning off exactly at zero is the failure case
It sounds ideal, but it is the worst case. Open the switch precisely at the current zero and there is no current left, so nothing recharges the node, and the opposite switch turns on into the full bus. The cost is the node's own charge dumped through the device that closes on it, ½·C·V² on the C_o(tr) above: 77 µJ per device at 440 V, 307 µJ for a leg of four at 3.18 nF, and about 603 W across a full bridge's four hard turn-ons per cycle at 490 kHz [derived, all three].
That is a different loss from the 440 µJ on the ZVS page. That figure is Q_rr × V at a Q_rr of 1 µC, and it belongs to the late case, where the opposite diode conducted first and the closing device then has to sweep out the recovered charge. Here no diode conducted, so there is no recovered charge and the loss is capacitive only. Per device it is 440 against 65, nearly seven times, so using the late figure here would overstate the penalty.
ZCS and ZVS trade against each other. Soft switching needs some current left over at turn-off, and the lead is what provides it.
The lead itself comes from a coil in series with the feedback burden resistor. Which coil to use has a surprisingly thin paper trail, three worries that turn out to be unfounded, and one failure that keeps happening.
The algorithm
1. measure T_d (short the inductor out and look)
2. compute T_ZVS (from C_o(tr) and your dead time)
3. L = R · tan(360° · f · (T_d + T_ZVS)) / (2·pi·f)
4. check: 45 degrees preferred, 60 maximum
5. if it will not fit, make the driver faster rather than the coil largerPeople skip step five. The 60 in step four is davekni's: with an ordinary UD2.x lead input the theoretical maximum is 90 degrees and the practical upper limit is about 60. The tangent is what makes it a ceiling, not the signal. At 490 kHz into 51 Ω, going from 45 to 60 degrees gains 85 ns and costs 12.1 µH. Going from 60 to 75 gains the same 85 ns and costs 33.1, nearly three times the wire for the same nanoseconds [derived, L = R·tan(phi)/(2·pi·f) at each angle]. Past 60 each nanosecond gets expensive, and the fix is a shorter delay chain rather than more inductance.
An earlier version gave a different reason, that the amplitude across the network had collapsed by then. That is backwards. The network is fed from a current transformer, so its voltage grows with the inductor, and loneoceans picks a large signal on purpose for that reason.
On a real machine, the floor from step 2 has to be recomputed at each frequency rather than carried across. On the reference build the cold chain is 190 ns and the ZVS floor is 91 ns at 490 kHz but 87 at the 519.1 kHz start of the ramp, so the two sums are 281 ns and 277, which give 49.6° and 51.8° [derived, 360·f·(T_d + T_ZVS) at each]. An earlier version printed 50.5 for the second, which is the 490 kHz floor read at the ramp's own frequency. The per-frequency floor is on the ZVS page and is what the site's calculator uses.
For a warm bridge we have two routes, and they give different answers. The model behind these figures expects a 218 ns chain, 28 ns more than the 190, which gives 52.6° and 55.1°. Scaling t_d(off) by the 30 per cent derived above adds 34.5 ns instead, giving 53.7° and 56.3° [derived, both routes, on the same two floors]. They are roughly a degree apart, and neither reaches 60. The figures 52.6 and 55.7 used to stand here as though they followed from the 30 per cent; they follow from the 218. Either way the preferred 45 is passed at every corner and the 60 is approached from below at the worst one. Treat the 45 to 60 band as a design range, not a target you hit.
What people actually fit
The Coilcraft 7M3 slug-tuned series, by device type. The device pairings are Gao Guangyan's, on his UD2.7 page, which is the only place they are published. The inductance spans are not his. They are Coilcraft's own L min and L max, from document 112, "Slot Seven" 7 mm Tunable Inductors, where all six of these rows read at 2.5 MHz:
- 7M3-123, 9 to 15 µH: works well with TO-247 IGBTs.
- 7M3-153, 11 to 19 µH.
- 7M3-223, 17 to 28.
- 7M3-333, 25 to 41.
- 7M3-393, 29 to 49: works well with CM200 and CM300 bricks.
- 7M3-563, 42 to 70.
Do not plan a board around being able to buy these, but "discontinued" is more than the record supports. What we have is faraday relaying Coilcraft's product quality supervisor on HVF 317: the coils "have been in production since the 60's", the coil form material changed a few years before 2018 to a glass filled one, and Coilcraft "are definetly not going to redesign the slot 7 style inductor as the demand is too low to justify it". An earlier version called the series end of life after forty years with no direct replacement in the current portfolio. No source we can fetch states either the age or the lack of a replacement, and the years since the sixties are more than forty, so both are out and the status is unknown.
The generation before it, from Ward's own bill of materials for the UD2.1 revB, was the Coilcraft SLOT TEN-5-09 and TEN-5-10. Coilcraft's document 113, "SLOT TEN" 10 mm Tunable Inductors, gives the 5-09 as 16 µH minimum, 42 maximum and 29.4 nominal and the 5-10 as 25, 60 and 42.3, both read at 2.5 MHz. Style 5 is what that document calls "Shielded with Ferrite Core and Sleeve", and its selection guide gives style 5 an electrostatic shield and a magnetic shield listed as ferrite, meaning the ferrite core sits in a ferrite sleeve.
Ward's original specification, since it settles an argument
From the UD2.1 revB schematic, dated March 2011:
- L1 = "10 to 60 µH", with a three pin header to short it out.
- R1 = 51 Ω, 2 W, the feedback burden.
- C32 = 150 pF across that burden.
- R17 = 5.1 Ω, 0.5 W, the overcurrent burden, on a separate transformer.
That clears up the 51 against 5.1 confusion. The 51 is the feedback burden and the only resistor L1 works against. The 5.1 is the overcurrent burden on a different ring and has nothing to do with the lead.
Ward never published his reasoning. There are no schematics or BOMs from him for the UD2.5, 2.7 or 2.9; his files stop at the 2.1 revB. Step 3 uses only the phase angle of a series RL network, arctan(XL/R), which is ordinary circuit theory and not anybody's design rule.
Mount it on the board
faraday, on HVF 317: because it was dangling there it seemed to be picking up enough EMF from the tesla coil that the signal going to the comparator got corrupted.
He adds "I could be wrong on this, but that's what I remember", so take it as one builder's recollection rather than a diagnosis. No one in that thread contradicts it, and no one reports trying it either.
If you wind your own, use a toroid, which closes its field, rather than an air coil. Daniel Marks (profdc9) wound his on empty Slot 7 forms off eBay and got "about 70 turns to get up to 50-60 uH inductance, which is adjustable by about 20 to 30%", in the same thread. His other option is a bank of fixed inductors in series with a jumper across each, which has the advantage that fixed parts publish an Irms and an Isat.
The one failure that repeats
It is mechanical: the tuning slug.
faraday, April 2018, on HVF 317: if I try to turn the slug down very far, not even close to bottoming, into the inductor, either the slug or the ceramic tuning tool will fracture.
Coilcraft's own explanation, via their product quality supervisor and relayed in the same post: they could not get the old coil form material a few years earlier and had to switch to a glass filled one, which is not as smooth, so the ferrite sticks to it. The tool supplier changed too, and three replacement tools were sent, of which one nearly fitted.
profdc9 cracked a bit off one. Turn them gently and do not run them to the stop.
Three worries that are not real
"One amp of feedback current is an overload." In fact it is the design target of the whole UD2.x family. loneoceans aims for about 1 A of feedback current and picks the CT ratio to suit, so a bridge expected to run at 500 A peak gets a 500:1 transformer. WaskaLabs give the same rule of thumb for the UD2.9-X, "to keep currents around 1A at the max current you plan to see through your primary". The UD3 is specified to handle 1 A peak regardless of topology. And Ward's 51 Ω at 2 W only makes sense at hundreds of milliamps RMS.
A driver from a different design runs at fifteen times that figure. Steve Conner's PLL driver manual specifies 33 turns into a 0.33 ohm burden for "~10mV/A and a maximum reading of about 500A", which puts 15.2 A through that burden at full scale [derived], and his brick variant, 100 turns into the same burden for 1500 A, puts 15.0 [derived]. Those are two configurations for machines three times apart, and what he holds constant is those fifteen amps and the five volts they make, not one amp. So the ampere is a convention of one driver family rather than a property of current transformers, which matches what the next paragraph finds from the other direction.
In the UD2.x family the ampere is the design current on both paths, and the two burdens are what differ. An earlier version briefly claimed the opposite, that what is held fixed is the volts across the burden and that an amp through the 51 Ω feedback part was not a thing a driver does. Both halves were wrong, and the designers say so themselves. loneoceans runs exactly that and gives the reason: "the phase lead circuit uses a relatively high voltage across the LR filter (~50+V across the 51R at 1A), and then fed through a resistor into a diode clamp circuit to make it into a reliable square signal", because a sinusoid into a comparator with a wide hysteresis band gives a variable delay and a large signal does not. Ward's protection path is the same ampere at the other end: a 5 Ω burden and a 1000 A limit is 5 V across it, and after "the diodes might drop .5V, or 1V drop total, so our output is really 4V. We would then set the comparator reference voltage to about 4V." At 1:1000 that trip is one amp of secondary current [derived]. So each burden is chosen for its path's job, large and clamped for the comparator's timing, small and compared for the trip, and the ampere runs through both. Ward adds a caveat that matters more than the figure: the reference "must be set experimentally", because the rectifier drop is not known in advance.
"The trim inductor will saturate, overheat or drift." Twenty years of forum archives contain no report of it. The eleven posts of HVF 317, a thread devoted to choosing these parts, do not mention current once. The builders there argue about the slug, the tuning tool and the footprint. The one time it was seriously proposed as a cause is HVF 3485, where CJ's phase lead stopped working as the bus voltage rose and the first of davekni's two guesses was "Core saturation of phase lead adjustment inductor". It was not. CJ traced it to paralleled 160N60 IGBTs with over 14 nF of C_iss against a 4.7 Ω resistor on each gate, and 12 Ω fixed it. That is a gate loop fault, and it has its own page. Two caveats stop that from clearing the parts on the list above. The coil davekni suspected was not one of them but a home-wound adjustable core, 56 turns of 0.15 mm enamelled wire covering 15 to 40 µH. And saturation was never tested and ruled out, only overtaken by a cure that worked. What the thread does show is that a threshold in bus voltage cannot tell a saturating core from a misbehaving gate loop, so scope the gate before you suspect the coil.
"These parts are only rated 100 mA." That figure traces to the Piconics ST series, and the trace checks out. Piconics' ST series sheet gives the ST303-3F an L range of 15 to 30 µH and an Idc Max of 40 mA, and the series a power dissipation of 200 mW max. But look at the part. Its mechanical drawing on that sheet is in inches and the largest dimension on it is 0.275, under 7 mm [derived, 25.4 mm per inch], turned by a #0-80 screw. That is a microwave component, and a 7 to 10 mm slug can is an order of magnitude more volume. Coilcraft's 142, 143 and 144, the same 10 mm class as the Slot Ten, do publish a current column: document 108 runs Irms from 13.4 A on the 1½ turn 142-01J08 down to 5.5 A on the 20½ turn 143-20J12, defined in its note 5 as "Average current for a 40°C rise above 25°C ambient". Take that as a bound on the mechanics rather than on your own part, because those are the 0.05 to 1.5 µH end of the catalogue and yours is a 29 µH winding. It does rule out the idea that a 10 mm tunable can is inherently a 100 mA part.
No current rating can be quoted for the parts on the list above because the makers do not give one. Document 112's 7M3 columns are part number, L min, L nom, L max, test frequency, Q min at L nom and DCR max. Document 113's Slot Ten columns do not even have DCR: part number, colour, L min, L max, L nom, Q min at L nom and test frequency. Neither document contains the words Irms, Isat, current or saturation anywhere. That is the convention for this class of part, and it is why the 142 series above can be quoted and these two cannot.
What this means at the bench
Before any of it, take the secondary out. Eastern Voltage Research's controller sheet makes that the first move and names what to put in its place: "The best approach to use when tuning a DRSSTC system is to remove the secondary coil, and test with a dummy load. An empty steel coffee can is a very good dummy load and readily available." It stands in the middle of the primary, where the secondary was. It absorbs the tank's energy and cannot build a voltage on a topload, so you can turn the setting through its whole range without anything flashing over while you are still looking for the edge. The same sheet warns that the can gets "excessively hot" and suggests filling it with water for the thermal mass, and notes you can do this at the real bus voltage or a reduced one off a variac.
The sheet does not mention that a steel can inside the primary is a shorted turn. Eddy currents in it push back against the primary's field, which pulls the tank frequency up from where it sits with the real secondary in place. So the setting the can gives you is a safe starting point, not the final one. Confirm it with the secondary back in and a short pulse.
- Wind the inductor the calculator gives you, less whatever the layout already contributes.
- Power up and put a probe on the bridge output.
- Look for a small bump at the end of the edge. That is the optimum, not a defect.
- Turn from small to large. Falling short is the more dangerous side.
- Repeat it warm. A hot bridge asks for more, and the setting moves.
On a ramped coil the frequency all this is computed at does not stay put, and a network holding a constant angle then delivers a changing number of nanoseconds. That is worked across a real ramp on the frequency page.
The phase lead calculator does the arithmetic and prints a zone rather than a single number, because a single number would claim more precision than the inputs have.