A full-bridge design in SiC power modules, CAB450M12XM3 or CAB500M17HM3 depending on the bus: a 900 V bus with 1200 V devices, or 1350 V with 1700 V devices in the buck stage. By September 2026 he was leaning toward the 1700 V modules, and toward APWM/PSFB modulation straight on the bridge instead of a separate buck stage. Three-phase input goes through a 6-pulse rectifier and boost front end near unity power factor. Secondary: a 250 mm fibreglass tube, roughly 130 turns of 1000-strand 0.05 mm litz over a 320 mm winding, landing around 3 mH and 6 kΩ. Gate drive is described as “injection locked, with double-zero phase lead,” plus a booster board to drive the bricks. It is the same architecture as the induction-heater and SSTC work, scaled up.
His target came down to around 150 kW average, with peaks out of the bridge in the 500 kW range during a burst. That is down from the early, admittedly unrealistic 500 kW *average* he'd first floated. No board was built as of his own September 2026 update: “the project has taken a backseat to life and more fundamental QCW research, but it's far from dead”. He was working on a gate-driver buffer board for initial testing. There are still no new photos beyond the original bulk-capacitor bank and the secondary under construction.
The opening post explains where the ambition came from and why he rejected the obvious modulation. The project began when he got access to “a warehouse with a 9 meter ceiling and an 800 A 3-phase 400 V feed”. A 500 kW average struck him as “so far beyond what anybody has done” that this coil became the stepping stone to it. Bulk storage is 2S11P or 3S7P of 15000 µF 450 V cans (82500 µF at 900 V or 35000 µF at 1350 V, 33.5 and 32 kJ). He records that the capacitors were donated by a forum member: “the project would be very difficult to complete without this donation”. Power-factor correction is to be a UCC28180, a part he had suggested to Steve Conner, “and he had good success with it”.
On the modulation, his reasoning in that 2025 post goes against the techniques he is best known for: “I looked at LDPSFB and APWM, but turn-off losses get problematic when using SiC bricks, due to their much greater turn-off losses compared to discrete parts”. He names two reasons. The product of Rds(on) and loop inductance is far higher than for discretes, and so is the Rg(int)×Rds(on) product. With a stock of SiC bricks in hand he concluded it “makes most sense here to use a buck-based modulator and operate the main bridge close to ZCS”, which also gives “a second layer of overcurrent protection if done correctly”. By September 2026, as noted above, he had moved back toward APWM/PSFB on the bridge. The two positions are a year apart and do not contradict each other.
The bricks have a thread of their own. He bought Cree-branded modules on eBay “without much info”, gambling that they were MOSFET half-bridges and not diodes. Opening one confirmed that they carry eight CPM3-1700-R020E dies of an early generation, with lower Rds(on) and higher gate capacitance than the nominal figures. That difference is what had misled him. The built-in temperature sensor turned out to be a PT500 RTD, not an NTC. In August 2026 he came back to them: “I’m making a gate driver to see how fast I can drive them and to mesure Eoff under soft turn-on conditions”. This is the buffer board mentioned above, now with a measurement in view.
Sources
- highvoltageforum.net: QCW II; Beyond Reason
- highvoltageforum.net: QCW II, the opening post and preliminary specs
- highvoltageforum.net: the mystery Cree bricks, and the gate driver he is building for them (2024-2026)
This is the card from the driver tree, written from what the builder published. Send corrections through the forum.