[ §1 · power stage ]

Snubber capacitance, and the bet it makes on ZVS

Win it and the energy returns to the tank for nothing. Lose it and half CV squared goes into the die every transition, which doubles the penalty for missing.

CommonGnd4 August 20263 min read

A snubber capacitor across a leg is not insurance. It is a bet, and the payoff depends entirely on whether you actually achieve zero voltage switching.

ZVS achieved. The snubber's energy returns to the tank. It costs nothing.
ZVS missed. CV²/2 goes into the die, every transition.

For four 470 pF per leg at 440 V that is 182 µJ per transition, which comes to 50 W at 14 per cent duty across both legs of a full bridge at 490 kHz. The snubber doubles the penalty for failing.

The transistor snubbers itself

Before adding any, look at what is already there:

C_o(tr) = 675 pF per device   (IPW65R080CFD)
t_f = 6 ns
dV during the current fall = I·t/C = 35 A × 6 ns / 2.7 nF = 78 V

The current has already fallen while the voltage is still low. External capacitance adds little to that.

But the superjunction non-linearity is real

C_oss   = 215 pF   (at high V_DS)
C_o(tr) = 675 pF   (averaged across a 0 to 400 V transition)

A spread of 3.1 times. In the middle of the swing the capacitance is at its minimum and there is still current flowing:

dV/dt_peak = I / (N · C_oss_min)

Worked: 35 A / (4 × 215 pF) = 41 V/ns against a datasheet limit of 50. That is 81 per cent of the rating on a device that is behaving normally.

This is the same effect Weston describes when he says superjunction FETs are poor in high frequency resonance: a non-linear lossy Coss gives voltage spikes and lower efficiency even under ZVS.

The main defence against dV/dt pickup on the gate is a negative gate rail, not a snubber. Reaching for capacitance to fix a gate problem is how the 50 W above gets paid for nothing.

So the rule has two walls

The dead time says the capacitance must be smaller, because the charge has to be moved within it. dV/dt ruggedness says it must not be too small. The optimum is where they meet.

For the worked example: 100 to 150 pF. Four hundred and seventy is already past the dead time wall.

And the external antiparallel diode that never conducts

body diode of the MOSFET, V_SD = 0.9 V   (IPW65R080CFD at 26.3 A)
external SiC Schottky, Vf     = 1.5 to 1.8 V

The external one will never turn on. The check takes a minute: measure both with a meter's diode range.

The exception is a device with a deliberately slow body diode. On a CFD, a Cool Fast Diode part, Q_rr is 1 µC against 10 or more for an ordinary superjunction, and no external diode is needed at all.

The figures here are calculations on published device data. Whether your bridge is achieving ZVS in the first place is the floor calculation, and it is the number this whole bet rides on.

snubberZVSMOSFET