An old-school build from the early days of the PLL SSTC, built from Steve Conner's own published driver. The schematic is titled "Original design by Steve Conner, scopeboy.com" and credits him, with no claim to original work. A CD4046 locks to antenna feedback from the topload through a type-1 phase comparator, and a potentiometer biasing the VCO input sets the operating phase. Because the chip oscillates on its own, the phase can be tuned offline before the coil is ever powered up. The first version (PLL SSTC 1, Nov 2007) ran a half bridge of unspecified FETs on a bare board next to the coil base. It was limited to half-wave-rectified mains to keep it from overheating, and had no audio modulation. After the original secondary detuned in storage, Uzzors2k rebuilt it as PLL SSTC 1.5 (Oct 2008). A ducting topload dropped the resonant frequency from 500 to 250 kHz, the driver moved to a full bridge of two IRFP450 pairs through a new 5-winding GDT, and the whole thing went into a wooden enclosure salvaged from an old spark-gap coil project. Both board photos are real period shots, not later restagings, taken on a Sony Ericsson K750i in 2007 and a Canon PowerShot A590 in 2008.
Schematics and photos
driver schematic (Steve Conner / scopeboy.com, as reproduced)
Sources
This is the card from the driver tree, written from what the builder published. Send corrections through the forum.