Commissioned rather than self-started. Czech Technical University in Prague asked Marek Novotný, who had just finished a working DRSSTC, for a tabletop SSTC small enough for an 80×30×30 cm shelf with no airflow. It was to sit in PlasmaLab at the faculty of nuclear sciences and physical engineering. He documented it in a multi-year build log on his own site, UHVLab, including months of failure before it worked. A borrowed UD2.7 board couldn't drive the gates cleanly at the small coil's 660 kHz. After four different gate-drive-transformer cores he gave up on that frequency and rewound for 391 kHz. Next he built his own antenna-feedback half-bridge driver, but antenna feedback was too noisy and position-sensitive. So he switched to a CD4046 phase-locked loop, building from a schematic he found on Jakub Tejišćák's site, and he credits both by name. With a PLL the drive frequency can be modulated directly by audio, so a $3 Bluetooth receiver board feeds music straight into the VCO input. First sparks: ~10 cm at 120 VAC. Three years later a transistor failure exposed a destructive bug. An LTSpice check showed that the under-voltage/over-temperature lockout left one IGBT's gate charge with nowhere to discharge, over 14 kW of simulated peak loss on the stuck switch. He fixed it with a GDT winding dedicated to dumping residual gate charge to ground. Separately he found that the CD4046's output phase could be fine-tuned with its R1 center-frequency resistor, a trick from a third credited source, Tefatronix. Final spec: half bridge of IRFP460s, CD4046 PLL, 481 kHz, three selectable power modes (50 Hz / 100 Hz / CW) reaching 1 kW, and roughly 10 cm sparks from the secondary in CW mode.
Schematics and photos
reference: Jakub Tejišćák's PLL driver schematic
Sources
This is the card from the driver tree, written from what the builder published. Send corrections through the forum.