The same builder as the half- and full-bridge SSTCs elsewhere in the tree, with design contributions again credited to a separate forum contributor, "sifun." The full bridge has two IRGP50B60PD1 IGBTs per side (eight total), sized for the current a ramp demands. It is switched through a predictive ("predikter") driver stage that avoids hard switching. The ramp comes off a buck converter on the bus, with one addition. A boost stage first pumps the input up to about 430 V to make up for the bus capacitors' droop during the pulse, instead of oversizing the capacitor bank to cover it. Measured: 300 A primary current, a pump time of roughly 20 ms, over 400 J and 60+ kW peak per pulse, and streamers up to 230 cm.
Schematics and photos
block diagram (Zerg, QCW DRSSTC)
Sources
This is the card from the driver tree, written from what the builder published. Send corrections through the forum.