A bachelor’s thesis at Czech Technical University in Prague, Faculty of Electrical Engineering, supervised by Martin Kněnický and defended in June 2020. The coil is inherited, and the thesis says so. The flat-wound, tapped primary, the secondary and the frame come from an earlier CTU thesis by Karel Lipkovský. All the electronics are new. Unlike the rest of this cluster, the driver uses a phase-locked loop instead of shaping a current-transformer signal straight into the gates. He argues that the extra circuitry gives a bridge that cannot be dragged outside set frequency limits, and a board that works unchanged on an SSTC with no tuned primary. A jumper bypasses the loop and drives from the feedback directly, so the board can run either way.
The loop is a 74HC4046. He judged its built-in phase comparators unsuitable, so the comparator is built outside the chip from a D flip-flop and a 74HC4053 analogue switch around the chip’s VCO. The same switch parks the VCO at a preset start frequency whenever the bridge is disabled. Feedback is two 10 ns LT1016 comparators on a 1:1020 current-transformer chain, with a trimmable delay compensation of 90 ns to 1 µs in front of the loop. Current limiting is by skipping cycles. An over-current latch withholds drive for the next cycle, and a second jumper sets when it re-arms. It can re-arm on the following oscillator cycle (true cycle skipping, with part of the tank energy flowing back while the bridge keeps switching at current zero). Or it can stay off until the next interrupter pulse, the classic behaviour. The gates are driven through TC4429s into complementary FDD8424 MOSFET pairs and gate-drive transformers. The full bridge uses HGTG30N60A4D IGBTs, two in parallel per switch, with a varistor across each. The gate-drive and current transformers are both wound from UTP cable on Ferroxcube toroids.
The burst arrives over 15 m of fibre (HFBR-1523 to HFBR-2524) through an auxiliary board with a 2.2 s soft-start timer and a pulse-length limiter. The interrupter is an Arduino Nano giving pulses up to about 387 µs, with audio modulation in its second firmware. He backs the cycle skipping with numbers. Long interrupter pulses never bring the primary current to a value dangerous to the IGBTs, and the discharges are as long as a short-pulse DRSSTC’s at lower current. It was tested for over an hour continuously at pulses beyond 380 µs and more than 2 kVA drawn, with the heatsink holding around 40 °C under a fan. In a closing note he names the next change he would make: isolated gate drivers in place of the transformer.
Sources
This is the card from the driver tree, written from what the builder published. Send corrections through the forum.