IGBT and MOSFET switch thermals
How hot the bridge runs, from what you know about your coil: the peak current, how long a burst is and how many come a second, and one figure from the first page of the datasheet, taken hot. The check is davekni's: work out how much thermal resistance you can afford instead of guessing at a heatsink.
whole bridge113 Waveraged at 14.00 % duty, 8 devices
per device, in a burst101 W304 W in the last cycle at 160 A
transient Z_th0.617 K/Wover 2000 µs for ΔT 100 K
duty = burst length × bursts a second (cannot pass 100 %)
per device, at the peak: RMS = I_pk/2/n average = I_pk/π/n
IGBT P = V_CE(sat) · I_avg MOSFET P = I_RMS² · R_DS(on)
burst average: rings up × ⅔ (IGBT) or × ½ (MOSFET), Conner's rule
QCW ramp × ½ or × ⅓ (linear) steady × 1
allowed Z_th(pulse) = ΔT / P_end allowed R_th(steady) = ΔT / P_average
P_end = P_peak × n·B(n,3/2): the burst's END heats the junction most
(steady 1; rings up π/4 IGBT, 2/3 MOSFET; QCW 2/3 IGBT, 8/15 MOSFET)Switching loss is taken as zero. With the phase lead set, the bridge turns off near zero current and that loss is small; when it is not set, the loss depends on how far off it is, and none of the inputs here describe that. Read every figure on this page as a floor: if zero-current switching fails, the margin is gone. That is another reason to set the phase lead generously. The anti-parallel diodes are not counted either.
“Rings up” is typical, not a bound. It is Steve Conner's rule, and our circuit simulation of a DRSSTC burst found it about right in four bursts out of five. A coil with a heavy arc load on long bursts reaches its peak early and stays near it. There the loss is up to half as much again as the rule says, and steady is the safe choice. Light load on short bursts runs a little cooler than the rule. Ramped bus means a QCW: the current climbs with the bus through the ramp, taken as a straight line from zero, so a ramp that starts high sits between it and steady.
Where the one datasheet figure comes from. For an IGBT, V_CE(sat) at the hottest junction temperature the datasheet gives (125, 150 or 175 °C), read at your peak current on the output characteristic if the headline figure is for a smaller current. For a MOSFET, R_DS(on) at the hot junction, which for a silicon part is commonly two to three times the 25 °C headline (less for silicon carbide). The cold figure understates the loss by that much.
Check the allowed Z_th against the transient thermal impedance curve in the datasheet at your pulse width, not against the static R_th(j-c).
ΔT is the input you have most freedom over. It defaults to 100 K, which is davekni's, a 150 °C die over a 50 °C heatsink. A smaller rise gives a longer life, and a pulse rating is a temperature covers why.
davekni's rule of thumb for the order of magnitude: devices fail at about 4× the continuous or 2× the pulsed rated current.